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ST
Sitronix
INTRODUCTION
drive liquid crystal, it is possible to make a display system with the fewest components.
ST7541
4 Gray Scale Dot Matrix LCD Controller/Driver
ST7541 is a driver & controller LSI for 4-level gray scale graphic dot-matrix liquid crystal display systems. This chip can connect directly to a microprocessor which supports: Serial Peripheral Interface (SPI), IIC or 8-bit parallel interface. Display data stores in an on-chip display data RAM of 128 x 129 x 2 bits. It performs display data RAM read/write operation with no external operating clock to minimize power consumption. In addition, because it contains power supply circuits necessary to
FEATURES
4-level Gray Scale
- Display with PWM and FRC Methods DDRAM Data [2n:2n+1] 2n 0 0 1 1 (Accessible column address, n = 0~127) 2n + 1 0 1 0 1 Gray Scale White Light gray Dark gray Black
Driver Output Circuits
128 segment outputs / 128+1 common outputs
On-chip Low Power Analog Circuit
- On-chip oscillator circuit - Voltage booster (x3, x4, x5 or x6) - Voltage regulator (temperature coefficient: -0.144%/C, or external input) - On-chip electronic contrast control function (64 steps X 8) - Voltage follower (LCD bias : 1/5 to 1/12)
Applicable Duty Ratios
- Various partial display - Partial window moving & data scrolling
On-chip Display Data RAM
- Capacity: 128 x 129 x 2= 33,024 bits
Microprocessor Interface
- 8-bit bi-directional parallel interface supports 6800-series or 8080-series MPU - 4-line serial interface (4-Line SPI) - 3-line serial interface (3-Line 8-bit SPI) - IIC serial interface
Operating Voltage Range
- Supply voltage (VDD): 1.8 to 3.3V - Supply voltage (VDD2): 2.4 to 3.3V - LCD driving voltage (VLCD = V0 - VSS): 3.5 to 15.0 V
Package Type
- Application for COG
ST7541 ST7541i
6800 , 8080 , 4-Line , 3-Line interface (without IIC interface) IIC interface
Sitronix Technology Corp. reserves the right to change the contents in this document without prior notice.
Ver 1.9
1/78
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ST7541
ST7541 Pad Arrangement (COG)
Chip Size: 12,575 um x 1,220 um Bump Pitch: PAD NO 1 ~ 229, 353 ~ 385: 55 um (COM/SEG), PAD NO 230 ~ 338: 75 um (I/O) ,PAD NO 339 ~ 352: 75 um (I/O) , PAD 338 ~ 339 : 81um Bump Size: PAD NO 1 ~ 196, 218 ~ 229, 353 ~ 364 : 35(x) um x96(y) um PAD NO 230 ~ 352 : 55(x)um x60(y) um Bump Height: 17 um (Typ) Chip Thickness: Part Number Thickness 635 um (default) 480 um 300 um PAD NO 197 ~ 217, 365 ~ 385 : 96(x) um x35(y) um
ST7541-G ST7541-G2 ST7541-G4
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Pad Center Coordinates
PAD No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 Pin Name COM30 COM29 COM28 COM27 COM26 COM25 COM24 COM23 COM22 COM21 COM20 COM19 COM18 COM17 COM16 COM15 COM14 COM13 COM12 COM11 COM10 COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM0 COMS1 SEG0 SEG1 SEG2 X 5096 5041 4986 4931 4876 4821 4766 4711 4656 4601 4546 4491 4436 4381 4326 4271 4216 4161 4106 4051 3996 3941 3886 3831 3776 3721 3666 3611 3556 3501 3446 3391 3336 3281 3226 Y 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 PAD No. 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 Pin Name SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 X 3171 3116 3061 3006 2951 2896 2841 2786 2731 2676 2621 2566 2511 2456 2401 2346 2291 2236 2181 2126 2071 2016 1961 1906 1851 1796 1741 1686 1631 1576 1521 1466 1411 1356 1301 Y 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556
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PAD No. 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 Pin Name SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 SEG62 SEG63 SEG64 SEG65 SEG66 SEG67 SEG68 SEG69 SEG70 SEG71 SEG72 X 1246 1191 1136 1081 1026 971 916 861 806 751 696 641 586 531 476 421 366 311 256 201 146 91 36 -19 -74 -129 -184 -239 -294 -349 -404 -459 -514 -569 -624 Y 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 PAD No. 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 Pin Name SEG73 SEG74 SEG75 SEG76 SEG77 SEG78 SEG79 SEG80 SEG81 SEG82 SEG83 SEG84 SEG85 SEG86 SEG87 SEG88 SEG89 SEG90 SEG91 SEG92 SEG93 SEG94 SEG95 SEG96 SEG97 SEG98 SEG99 SEG100 SEG101 SEG102 SEG103 SEG104 SEG105 SEG106 SEG107 X -679 -734 -789 -844 -899 -954 -1009 -1064 -1119 -1174 -1229 -1284 -1339 -1394 -1449 -1504 -1559 -1614 -1669 -1724 -1779 -1834 -1889 -1944 -1999 -2054 -2109 -2164 -2219 -2274 -2329 -2384 -2439 -2494 -2549 Y 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556
Ver 1.9
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PAD No. 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 Pin Name SEG108 SEG109 SEG110 SEG111 SEG112 SEG113 SEG114 SEG115 SEG116 SEG117 SEG118 SEG119 SEG120 SEG121 SEG122 SEG123 SEG124 SEG125 SEG126 SEG127 Reserve Reserve Reserve Reserve COM64 COM65 COM66 COM67 COM68 COM69 COM70 COM71 COM72 COM73 COM74 X -2604 -2659 -2714 -2769 -2824 -2879 -2934 -2989 -3044 -3099 -3154 -3209 -3264 -3319 -3374 -3429 -3484 -3539 -3594 -3649 -3704 -3759 -3814 -3869 -3924 -3979 -4034 -4089 -4144 -4199 -4254 -4309 -4364 -4419 -4474 Y 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 PAD No. 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 Pin Name COM75 COM76 COM77 COM78 COM79 COM80 COM81 COM82 COM83 COM84 COM85 COM86 COM87 COM88 COM89 COM90 COM91 COM92 COM93 COM94 COM95 COM96 COM97 COM98 COM99 COM100 COM101 COM102 COM103 COM104 COM105 COM106 COM107 COM108 COM109 X -4529 -4584 -4639 -4694 -4749 -4804 -4859 -4914 -4969 -5024 -5079 -5134 -5189 -5244 -5299 -5354 -5409 -5464 -5519 -5574 -5629 -6234 -6234 -6234 -6234 -6234 -6234 -6234 -6234 -6234 -6234 -6234 -6234 -6234 -6234 Y 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 556 550 495 440 385 330 275 220 165 110 55 0 -55 -110 -165
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PAD No. 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 Pin Name COM110 COM111 COM112 COM113 COM114 COM115 COM116 COM117 COM118 COM119 COM120 COM121 COM122 COM123 COM124 COM125 COM126 COM127 COMS2 T9 VDD PS0 PS1 PS2 VSS CSB CSB RST RST A0 A0 RW_WR RW_WR E_RD E_RD X -6234 -6234 -6234 -6234 -6234 -6234 -6234 -5418 -5363 -5308 -5253 -5198 -5143 -5088 -5033 -4978 -4923 -4868 -4813 -4729 -4654 -4579 -4504 -4429 -4354 -4279 -4204 -4129 -4054 -3979 -3904 -3829 -3754 -3679 -3604 Y -220 -275 -330 -385 -440 -495 -550 -556 -556 -556 -556 -556 -556 -556 -556 -556 -556 -556 -556 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 PAD No. 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 Pin Name D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7 VDD VDD VDD VDD VDD VDD VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 X -3529 -3454 -3379 -3304 -3229 -3154 -3079 -3004 -2929 -2854 -2779 -2704 -2629 -2554 -2479 -2404 -2329 -2254 -2179 -2104 -2029 -1954 -1879 -1804 -1729 -1654 -1579 -1504 -1429 -1354 -1279 -1204 -1129 -1054 -979 Y -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574
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PAD No. 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 Pin Name VDD2 VDD2 VDD2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS VSS VSS VSS VSS VSS TA TB MF2 MF1 MF0 DS0 DS1 VDD VOUT_OUT VOUT_OUT X -904 -829 -754 -679 -604 -529 -454 -379 -304 -229 -154 -79 -4 71 146 221 296 371 446 521 596 671 746 821 896 971 1046 1121 1196 1271 1346 1421 1496 1571 1646 Y -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 PAD No. 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 Pin Name VOUT_OUT VOUT_OUT VOUT_OUT VOUT_OUT VOUT_IN VOUT_IN VOUT_IN VOUT_IN VOUT_IN VOUT_IN T[8] T[7] T[6] T[5] T[4] T[3] T[2] T[1] T[0] VDD REF VSS VEXT VDD INTRS VSS OSC1 OSC1 VDD VR VR V4 V3 V2 V1 X 1721 1796 1871 1946 2021 2096 2171 2246 2321 2396 2471 2546 2621 2696 2771 2846 2921 2996 3071 3146 3221 3296 3371 3452 3527 3602 3677 3752 3827 3902 3977 4052 4127 4202 4277 Y -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574 -574
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PAD No. 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 Pin Name V0 V0 COM63 COM62 COM61 COM60 COM59 COM58 COM57 COM56 COM55 COM54 COM53 COM52 COM51 COM50 COM49 COM48 X 4352 4427 5340 5395 5450 5505 5560 5615 5670 5725 5780 5835 5890 5945 6234 6234 6234 6234 Y -574 -574 -556 -556 -556 -556 -556 -556 -556 -556 -556 -556 -556 -556 -550 -495 -440 -385 PAD No. 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 Pin Name COM47 COM46 COM45 COM44 COM43 COM42 COM41 COM40 COM39 COM38 COM37 COM36 COM35 COM34 COM33 COM32 COM31 X 6234 6234 6234 6234 6234 6234 6234 6234 6234 6234 6234 6234 6234 6234 6234 6234 6234 Y -330 -275 -220 -165 -110 -55 0 55 110 165 220 275 330 385 440 495 550
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BLOCK DIAGRAM
SEG0 TO SEG127 COM0 TO COM128
VDD
V0 V1 V2 V3 V4 SEGMENT DRIVERS COMMON DRIVERS
VSS
DATA LATCHES V/F Circuit
COMMON OUTPUT CONTROLLER CIRCUIT
V0 VR INTRS VEXT REF
FRC/PWM FUNCTION CIRCUIT RESET V/R Circuit
DISPLAY DATA RAM (DDRAM) [128X129X2]
OSCILLATOR TIMING GENERATOR DISPLAY ADDRESS COUNTER
OSC1
V/C Circuit ADDRESS COUNTER
VOUT_IN VOUT_OUT VDD2 VSS2
DATA REGISTER BUS HOLDER
INSTRUCTION REGISTER INSTRUCTION DECODER
MPU INTERFACE(PARALLEL & SERIAL)
RW_WR
MF0 MF1 MF2
A0 CSB /RST PS0 PS1 PS2
DS0 DS1
E_RD
DB6(SI)
DB7(SCL)
DB0 DB1 DB2 DB3 DB4 DB5
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PIN DESCRIPTION
POWER SUPPLY
Name VDD VSS VDD2 VSS2 VOUT_OUT Type Power Power Power Power Power Digital Power supply Ground Analog Power supply Ground Internal booster output. Left these pads open when using external power supply. Short VOUT_OUT with VOUT_IN when using internal booster. The power supply pads of internal regulator. Apply high voltage here for internal regulator. VOUT_IN Power If using external booster, VOUT_OUT must be open with internal booster programmed OFF (set register VC=0). If using internal booster, short VOUT_OUT with VOUT_IN together. LCD driver supply voltages. V1, V2, V3, V4 need the capacitor between with VSS. V0 V1 V2 V3 V4 Power Voltages should have the following relationship: V0 V1 V2 V3 V4 VSS When the internal power circuit is active, these voltages are generated as following table according to the state of LCD bias. LCD bias 1/N bias NOTE: N = 5 to 12 V1 (N-1) / N x V0 V2 (N-2) / N x V0 V3 (2/N) x V0 V4 (1/N) x V0 Description
LCD DRIVER SUPPLY
Name VR Type V0 voltage adjustment pin I It is valid only when on-chip resistors are not used (INTRS = "L") When using internal resistors (INTRS = "H"), open this pin Selects the external VREF voltage via the VEXT pin REF I REF = "H": using the internal VREF REF = "L": using the external VREF Externally input reference voltage (VREF) for the internal voltage regulator VEXT OSC1 I I It is valid only when REF is "L" When using internal voltage regulator, this pin must be open External OSC input pin, when using internal clock oscillator, connect OSC1 to VDD. Description
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SYSTEM CONTROL
Name Type INTRS = "H": use the internal resistors. INTRS = "L": use the external resistors. VR pin and external resistive divider control V0 voltage T[0] ~ T[9] Reserve MF[2:0] DS[1:0] TA, TB Test X I I I Test pins. Don' t use these pins. Please Open these pins. This pin must be OPEN Manufacturer ID code for reference, suggest set to [ MF2.MF1.MF0 = 0.0.0 ] Display size ID code for reference, suggest set to [ DS1.DS0 = 0.0 ] Test pins TA and TB must connect to Vss. Description Internal resistor select pin. This pin selects the resistors for adjusting V0 voltage level. INTRS I
MICROPROCESSOR INTERFACE
Name RST Type I Microprocessor interface select input pin PS2 L L PS[2:0] I L L H NOTE: *1. Reading of data or status is not available in serial interface modes (4-Line, 3-Line and IIC). *2. In 3-Line or 4-Line interface: DB[5:0], E_RD and RW_WR must be fixed to "H" or "L". *3. In IIC and 3-Line interface: A0 must be fixed to "H" or "L". CSB I Chip select input. Data/instruction I/O is enabled only when CSB is "L". When chip select is non-active, DB[7:0] will be high impedance. Register selection input. A0 I A0 = "H": DB[7:0] are display data. A0 = "L": DB[7:0] are control instruction. Read / Write execution control pin PS1 H MPU type 6800-series RW_WR R/W R/W = "H" : read; R/W = "L" : write. Write enable clock input pin. L 8080-series /WR The data on DB[7:0] are latched at the rising edge of the /WR signal. Description Read / Write control input pin. RW_WR I PS1 L H L H L PS0 H H L L L Interface mode Parallel 80 Parallel 68 3Line Serial 4Line Serial IIC Serial A0 A0 A0 A0 Data DB[7:0] DB[7:0] SID (DB7) SID (DB7) SDA Read/Write /RD, /WR E, R/W Write only Write only Read/Write Serial clock SCLK (DB6) SCLK (DB6) SCL Description Reset input pin. When RST is "L", initialization is executed.
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MICROPROCESSOR INTERFACE (continued)
Name Type Read / Write execution control pin PS1 MPU Type E_RD Description Read / Write control input pin. E_RD I H 6800-series E R/W = "H": When E is "H", DB[7:0] are in an output status; R/W = "L": DB[7:0] are latched at the falling edge of this signal. L 8080-series /RD Read enable clock input pin. When /RD is "L", DB[7:0] are in output status. Description
8-bit bi-directional data bus that is connected to the standard 8-bit microprocessor data bus. When chip select is not active (CSB=H), DB[7:0] will be high impedance. When the 3-Line/4-Line serial interface is selected (PS[2:0] = "000" or "010"): DB[0:5]: high impedance (connect to "H" or "L"); DB6: serial input clock (SCLK); DB7: serial input data (SID). DB[7:0] I/O When chip select is not active, DB[7:0] is high impedance. When the IIC serial interface is selected (PS[2:0] = "100"): DB7: serial clock input (SCL); DB[6:4]: serial data input (SDA_IN); DB[3:2]: serial data output (SDA_OUT). For acknowledge signal output in IIC interface; DB[1:0]: Is slave address (SA) bit1, 0, must connect to Vdd or Vss. *DB[6:2]: must be connected together as SDA signal of IIC interface. Note: 1. By connecting SDA_IN and SDA_OUT externally, the SDA line becomes fully IIC interface compatible. Separating acknowledge-output from serial data input is advantageous for chip-on-glass (COG) applications. In COG applications, the ITO resistance and the pull-up resistor will form a voltage divider which affects acknowledge-signal level. Larger ITO resistance will raise the acknowledge-signal level and system cannot recognize this level as a valid logic "0" level. By separating SDA_IN from SDA_OUT, the IC can be used in a mode which ignores the acknowledge-bit. For applications which check acknowledge-bit, it is necessary to minimize the ITO resistance of the SDA_OUT trace to guarantee a valid low level. 2. After VDD is turned ON, any MPU interface pins cannot be left floating.
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LCD DRIVER OUTPUTS
Name Type LCD segment driver outputs. The display data and frame signal control the output voltage of segment driver. SEG0 to SEG127 O Display Data H H L L LCD common driver outputs. The scan signal and frame signal control the output voltage of common driver. COM0 to COM127 O Scan Data H H L L COMS (COMS1,2) Frame + + Common driver output voltage VSS V0 V1 V4 VSS Frame + + Segment driver output voltage Normal display V0 VSS V2 V3 VSS Reverse display V2 V3 V0 VSS VSS Description
Display OFF, Power Saving
Display OFF, Power Saving O Common output for the icons.
The output signals of two pins are same. When not used, these pins should be left open.
Recommend ITO Resistance
PIN Name PS[2:0], REF, OCS1, INTRS, TA, TB T[9:0], VR, VEXT Vdd, Vdd2, Vss, Vss2 , VOUT_IN , VOUT_OUT SDA (SDA_IN & SDA_OUT) V0, V1 , V2 , V3 , V4 RST Note: 1. 2. 3. If using IIC interface mode, the resistance of SDA signal should be lower than 300 (if the system pull up resistor is 4.7K). The option setting to be "H" should connect to VDD. The option setting to be "L" should connect to VSS.
*1 *1
ITO Resistance No Limitation Floating <100 <300 <1K <500 <10K
CSB , E , R/W , A0 , DB[7:0]
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FUNCTIONAL DESCRIPTION
MICROPROCESSOR INTERFACE
Chip Select Input There is CSB pin for chip selection. The ST7541 can interface with an MPU when CSB is "L". When these pins are set to any other combination, A0, E_RD, and RW_WR inputs are disabled and DB0 to DB7 are to be high impedance. And, in case of serial interface, the internal shift register and the counter are reset. Parallel / Serial Interface ST7541 has five types of interface with an MPU, which are three serial and two parallel interfaces. This parallel or serial interface is determined by PS pin as shown in Table 1. Table 1 Parallel / Serial Interface Mode Type Parallel PS2 L L L Serial L H Parallel Interface (PS0 = "H") The 8-bit bi-directional data bus is used in parallel interface and the type of MPU is selected by PS1 as shown in Table 2. The type of data transfer is determined by signals at A0, E_RD and RW_WR as shown in Table 3. Table 2 Microprocessor Selection for Parallel Interface PS1 H L CSB CSB CSB A0 A0 A0 E_RD E /RD RW_WR R/W /WR DB0 to DB7 DB0 to DB7 DB0 to DB7 MPU bus 6800-series 8080-series PS1 H L L H L L PS0 H CSB CSB CSB CSB CSB Interface mode 6800-series MPU mode 8080-series MPU mode 3-Line SPI mode 4-Line SPI mode IIC SPI mode
Table 3 Parallel Data Transfer Common A0 H H L L 6800-series E_RD (E) H H H H RW_WR (R/W) H L H L 8080-series E_RD (/RD) L H L H RW_WR (/WR) H L H L Display data read out Display data write Register status read Writes to internal register (instruction) Description
NOTE: When E_RD pin is always pulled high for 6800-series interface, it can be used CSB for enable signal. In this case, interface data is latched at the rising edge of CSB and the type of data transfer is determined by signals at A0, RW_WR as in case of 6800-series mode.
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Serial Interface
Serial mode 3-Line SPI mode 4-Line SPI mode IIC SPI mode PS0 L L L PS1 L H L PS2 L L H CSB CSB CSB CSB A0 No used Used No Used
If A0 is not used it must be fixed either "H" or "L" 3-Line / 4-Line (PS[2:0] = "000" or "010") 3-Line and 4-Line serial interface are similar except the display data/command indication is controlled by commands (3-Line SPI mode) or by the register selection pin (A0, 4-Line SPI mode). When ST7541 is active (CSB="L"), serial data (DB7) and serial clock (DB6) inputs are enabled. When ST7541 is not active (CSB="H"), the internal 8-bit shift register and 3-bit counter are reset. The read operation is not supported in these modes. Serial data on SID is latched at the rising edge of serial clock on SCL. After the 8th serial clock, the serial input data on SID will be processed as 8-bit parallel data/command. When writing sequential display data, the DDRAM column address pointer will be increased by one automatically after each byte of DDRAM access. 4-Line SPI Mode (PS0 = "L", PS1 = "H", PS2 = "L") This mode uses A0 pin to indicate the input serial data on SID is display data (A0="H") or command (A0="L").
Figure 1. 4-line SPI Timing
3-Line SPI Mode (PS0 = "L", PS1 = "L" ,PS2= "L") This mode does not have an A0 pin to indicate the input serial data on SID is display data or command. The default input from MCU is command. The display data/command indication is controlled via software. The MCU send 2-byte command (Set Data Direction & Display Data Length) before the display data(s). These 2 commands are only used in 3-Line SPI mode. The first command "Set Data Direction" (11101000b) indicates MCU wants to transfer display data. The second command "Display Data Length" informs LCD driver the number of input data bytes. After receiving these two continuous commands, the following messages will be treated as display data rather than command. After the display data string is sent over, the following bytes are treated as commands (unless receiving another pair of Set Data Direction & Display Data Length commands). If data transfer is stopped during transmitting, it is not valid data. New data will be transferred serially with most significant bit first. NOTE: In spite of transmission of data, if CSB is disabled, the state will be terminated abnormally and next state is initialized.
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(1) Set Page and Column Address:
Action Set Page Address Set Column Address MSB Set Column Address LSB Action Set Data Direction (DDC) (3-Line SPI mode Only) Set Display Data Length (No. of DATA) DB7 1 0 0 DB7 1 D7 DB6 0 0 0 DB6 1 D6 DB5 1 0 0 DB5 1 D5 DB4 1 1 0 DB4 0 D4 DB3 P3 0 Y4 DB3 1 D3 DB2 P2 Y7 Y3 DB2 0 D2 DB1 P1 Y6 Y2 DB1 0 D1 DB0 P0 Y5 Y1 DB0 0 D0
(2) Set Data Direction and Set Display Data Length:
(3) This figure is example for 104 Data bytes to be transferred.
Figure 2. 3-Line SPI Timing (A0 is not used) IIC Interface (PS0 = "L", PS1 = "L", PS2= "H") IIC Interface uses two signals (Serial Data: SDA and Serial Clock: SCL) to communicate with MPU and other ICs or modules. It receives the command and data sent by MPU through SDA and SCL. Both SDA and SCL must connect to VDD by a pull-up resistor which drives SDA and SCL to "HIGH" when the bus is not busy. Data transfer can be initiated only when the bus is not busy. This interface supports writing command/data and reading acknowledge-bit. [ BIT TRANSFER ] One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse because changes on SDA while SCL is "HIGH" will be interpreted as START or STOP. Bit transfer is illustrated in Figure 3.
SDA SCLK
Data line stable Data Valid Change of data allowed
Figure 3. Bit transfer
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[ START AND STOP CONDITIONS ] When the bus is not busy, both SDA and SCL lines remain HIGH. A HIGH-to-LOW transition of SDA, while SCL is HIGH is defined as the START condition (S). A LOW-to-HIGH transition of SDA while SCL is HIGH is defined as the STOP condition (P). The START and STOP conditions are illustrated in Figure 4.
Figure 4. Definition of START and STOP conditions [ SYSTEM CONFIGURATION ] The system configuration is illustrated in Figure 5 and some word-definitions are explained below: l l l l l l l Transmitter: the device, which sends the data to the bus. Receiver: the device, which receives the data from the bus. Master: the device, which initiates a transfer, generates clock signals and terminates a transfer. Slave: the device addressed by a master. Multi-Master: more than one master can attempt to control the bus at the same time without corrupting the message. Arbitration: the procedure to ensure that, if more than one master tries to control the bus simultaneously, only one is allowed to do so and the message is not corrupted. Synchronization: procedure to synchronize the clock signals of two or more devices.
Figure 5. System configuration [ ACKNOWLEDGE ] Each byte of eight bits is followed by an acknowledge bit. The acknowledge bit is a HIGH signal put on SDA by the transmitter during the time when the master generates an extra acknowledge-related clock pulse. A slave receiver which is addressed must generate an acknowledge-bit, after the reception of each byte. The device that acknowledges must pull-down the SDA line during the acknowledge-clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge-related clock pulse (set-up and hold times must be taken into consideration). Acknowledgement on the IIC Interface is illustrated in Figure 6.
Figure 6. Acknowledgement on the 2-line Interface
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[ IIC INTERFACE PROTOCOL ] The IIC interface of ST7541 supports writing command/data to the addressed slaves on the bus. Before transferring any data on the bus, the target device(s) should be addressed first. Four slave addresses (0111100, 0111101, 0111110 and 0111111) are reserved for ST7541. The least significant 2 bits of the slave address is configured by connecting the inputs SA1 and SA0 to either logic 0 (VSS) or logic 1 (VDD). The IIC Interface protocol is illustrated in Figure 7. The IIC communication sequence is initiated with a START condition (S) set by the master, and then followed by a slave address. All slaves with the same specified address should acknowledge in parallel, all the others will ignore the bus transfer. After the acknowledgement of the slave address, one or more command words are followed. The command word(s) define the status of the addressed slaves. A command word consists of a control byte (which defines Co and A0) and a data byte. The last control byte is tagged with a cleared most significant bit (i.e. Co=0), and is followed by data byte(s) only. The A0 bit in the control byte defines whether the data byte(s) will be interpreted as command or as RAM data. Therefore, after the last control byte, either a series of display data bytes or a series of command data bytes may follow (depends on the A0 bit). If the A0 bit is set to 0, the command bytes will be decoded and execute. If the A0 bit of the last control byte is set to 1, the series of display data bytes will be stored in DDRAM. The data pointer is automatically increased by 1 after writing each byte of display data into DDRAM. The addressed slave makes the acknowledgement after receiving each byte of command or display data. At the end of transmission the bus master issues a STOP condition (P).
Figure 7. 2-line Interface protocol Co 0 1 Last control byte. Only a stream of data bytes is allowed to follow. This stream may only be terminated by a STOP or RE-START condition. Another control byte will follow the data byte unless a STOP or RE-START condition is received.
BUSY FLAG
The Busy Flag indicates whether the ST7541 is operating or not. When DB7 is "H" in read status operation, this device is in busy status and will accept only read status instruction. If the cycle time is correct, the microprocessor needs not to check this flag before each instruction, which improves the MPU performance.
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DATA TRANSFER
The ST7541 uses bus holder and internal data bus for data transfer with the MPU. When writing data from the MPU to on-chip RAM, data is automatically transferred from the bus holder to the RAM as shown in Figure 8. And when reading data from on-chip RAM to the MPU, the data for the initial read cycle is stored in the bus holder (dummy read) and the MPU reads this stored data from bus holder for the next data read cycle as shown in Figure 9. This means that a dummy read cycle must be inserted between each pair of address sets when a sequence of address sets is executed. Therefore, the data of the specified address cannot be output with the read display data instruction right after the address sets, but can be output at the second read of data. MPU signal A0 /WR D0 to D7 Internal signals /WR BUS HOLDER COLUMN ADDRESS N D(N) N D(N+1) N+1 D(N+2) N+2 D(N+3) N+3 N D(N) D(N+1) D(N+2) D(N+3)
Figure 8 Write Timing MPU signal A0 /WR /RD D0 to D7 Internal signals /WR /RD BUS HOLDER COLUMN ADDRESS N N D(N) D(N) D(N+1) D(N+2) D(N+1) D(N+2) N Dummy D(N) D(N+1)
Figure 9 Read Timing
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DISPLAY DATA RAM (DDRAM)
The Display Data RAM stores pixel data for the LCD. It is 129-row (17 pages by 8 bits) by 128-column addressable array. Each pixel can be selected when the page and column addresses are specified. The 129 rows are divided into 16 pages of 8 lines and the 17th page with a single line (DB0 only). Data is read from or written to the 8 lines of each page directly through DB0 to DB7. The display data of DB0 to DB7 from the microprocessor correspond to the LCD common lines. The microprocessor can read from and write to RAM through the I/O buffer. Since the LCD controller operates independently, data can be written into RAM at the same time as data is being displayed without causing the LCD flicker. Page Address Circuit It incorporates 4-bit Page Address register changed by only the "Set Page" instruction. Page Address 16 is a special RAM area for the icons and display data DB0 is only valid. The page address is set from 0 to 15, and Page 16 is for Icon page. Line Address Circuit This circuit assigns DDRAM a Line Address corresponding to the first line (COM0) of the display. Therefore, by setting Line Address repeatedly, it is possible to realize the screen scrolling and page switching without changing the contents of on-chip RAM. It incorporates 7-bit Line Address register changed by only the initial display line instruction and 7-bit counter circuit. At the beginning of each LCD frame, the contents of register are copied to the line counter which is increased by CL signal and generates the line address for transferring the 128-bit RAM data to the display data latch circuit. When icon is enabled by setting icon control register, display data of icons are not scrolled because the MPU can not access Line Address of icons. Segment Control Circuit This circuit controls the display data scan circuit. It allows the display data related commands (such as: Display ON/OFF, Reverse Display ON/OFF and Entire Display ON/OFF) without changing the data in the DDRAM. Column Address Circuit Command "Set Column Address MSB / LSB" will set 7-bit ([Y7:Y1]) of the internal column address and Y0 is set to "0". The internal column address (Y[7:0]) is increased by 1 after accessing (read or write) each byte of display data (refer to Figure 10). After the 2
nd
access (read or write), the Column Address will point to the next column) SEG 0 1 01H 2 02H 3 03H ... ... 124 7CH 125 7DH 126 7EH 127 7FH
Set Column Address [Y7:Y1] DDRAM Col. Address [Y7:Y0] Display data (MX=0) LCD panel display 00 1 01 1 02 1 03 0 04 0 05 1 06 0 07 0 ... ... ... F8 1 F9 1 FA 1 FB 0 FC 0 FD 1 FE 0 FF 0 Sequential Display Data Read/Write Direction 00H
Display data (MX=1) LCD panel display
0
0
0
1
1
0
1
1
... ...
0
0
0
1
1
0
1
1
Figure 10 The Relationship between the Column Address and The Segment Outputs
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LCD DISPLAY CIRCUITS
FRC (Frame Rate Control) and PWM (Pulse Width Modulation) Function Circuit ST7541 incorporates FRC function and PWM circuits to display a 4-level gray scale. The FRC function and PWM utilize liquid crystal characteristics whose transmittance is changed by an effective value of applied voltage. ST7541 provides palette-registers to assign the desired gray level. These registers are set by the instructions and the RST. 4FRC & 3FRC vs. 9PWM, 12PWM, 15PWM - Gray Scale Table of 4 FRC (Frame Rate Control) Gray scale level White Light gray Dark gray Black - Gray Scale Table of 3 FRC (Frame Rate Control) Gray scale level White Light gray Dark gray Black - Gray Scale Table of PWM (Pulse Width Modulation) Frame Parameter (FRn) Dec 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Hex 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 4-bit 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0(0/15) 1/15 2/15 3/15 4/15 5/15 6/15 7/15 8/15 9/15 10/15 11/15 12/15 13/15 14/15 1(15/15) Darker 0/12 15-PWM PWM width Note Brighter 0(0/12) 1/12 2/12 3/12 4/12 5/12 6/12 7/12 8/12 9/12 10/12 11/12 1(12/12) Darker This field is OFF level 0/9 This field is OFF level 12-PWM PWM width Note Brighter 0(0/9) 1/9 2/9 3/9 4/9 5/9 6/9 7/9 8/9 1(9/9) Darker 9-PWM PWM width Note Brighter MSB (DB7 to DB4) 2nd FR (FR2) XXXX 2nd FR (FR2) XXXX 2nd FR (FR2) XXXX 2nd FR (FR2) XXXX LSB (DB3 to DB0) 1st FR (FR1) 3rd FR (FR3) 1st FR (FR1) 3rd FR (FR3) 1st FR (FR1) 3rd FR (FR3) 1st FR (FR1) 3rd FR (FR3) MSB (DB7 to DB4) 2nd FR (FR2) 4th FR (FR4) 2nd FR (FR2) 4th FR (FR4) 2nd FR (FR2) 4th FR (FR4) 2nd FR (FR2) 4th FR (FR4) LSB (DB3 to DB0) 1st FR (FR1) 3rd FR (FR3) 1st FR (FR1) 3rd FR (FR3) 1st FR (FR1) 3rd FR (FR3) 1st FR (FR1) 3rd FR (FR3)
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Oscillator This is on-chip Oscillator without external resistor. When the internal oscillator is used, this pin must connect to VDD; when the external oscillator is used, this pin could be input pin. This oscillator signal is used in the voltage converter and display timing generation circuit. Display Timing Generator Circuit This circuit generates some signals to be used for displaying LCD. The display clock, CL (internal), generated by oscillation clock, generates the clock for the line counter and the signal for the display data latch. The line address of on-chip RAM is generated in synchronization with the display clock and the display data latch circuit latches the 128-bit display data in synchronization with the display clock. The display data, which is read to the LCD driver, is completely independent of the access to the display data RAM from the microprocessor. The display clock generates an LCD AC signal (M) which enables the LCD driver to make an AC drive waveform, and also generates an internal common timing signal and start signal to the common driver. The frame signal or the line signal changes the M by setting internal instruction. Driving waveform and internal timing signal are shown in Figure 11.
128 129 1 2 3 4 5 6 7 8 9 10 11 12 121 122 123 124 125 126 127 128 129 1 2 3 4 5
CL(Internal) FR(Internal) M(Internal)
V0 V1 V2 V3 V4 VSS V0 V1 V2 V3 V4 VSS V0 V1 V2 V3 V4 VSS
COM0
COM1
SEGn
Figure 11 2-frame AC Driving Waveform (Duty Ratio: 1/129)
128
129
1
2
3
4
5
6
7
8
9
10
11
12
120
121
122
123
124
125
126
127
128
129
1
2
3
4
CL(Internal)
FR(Internal) M(Internal)
V0
COM0
V1 V2 V3 V4 Vss V0 V1 V2 V3 V4 Vss V0 V1 V2 V3 V4 Vss
COM1
SEGn
Figure 12 N-Line Inversion Driving Waveform (N=5,Duty Ratio=1/129)
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LCD DRIVER CIRCUIT
This driver circuit is configured by 129-channel common drivers and 128-channel segment drivers. This LCD panel driver voltage depends on the combination of display data and M signal.
M
COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7
VDD VSS
V0 V1 V2 V3 V4 VSS V0 V1 V2 V3 V4 VSS V0 V1 V2 V3 V4 VSS V0 V1 V2 V3 V4 VSS V0 V1 V2 V3 V4 VSS V0 V1 V2 V3 V4 VSS -V4 -V3 -V2 -V1 -V0 V0 V1 V2 V3 V4 VSS -V4 -V3 -V2 -V1 -V0
COM0
COM1
COM8 COM9 COM10 COM11 COM12 COM13 COM14
COM2
SEG0
SEG 0 1 2 3 4
SEG1
COM0 to SEG0
COM0 to SEG1
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Partial Display on LCD ST7541 realizes the Partial Display function on LCD with low-duty driving for saving power consumption and showing the various display duty. To show the various display duty on LCD, LCD driving duty and bias are programmable via the instruction. And, built-in power supply circuits are controlled by the instruction for adjusting the LCD driving voltages. The partial display duty ratio could be set from 16 ~ 128. If the partial display region is out of the Max. Display range, it would be no operation.
-COM0 -COM1 -COM2 -COM3 -COM4 -COM5 -COM6 -COM7 -COM8 -COM9 -COM10 -COM11 -COM12 -COM13 -COM14 -COM15 -COM16 -COM17 -COM18 -COM19 -COM20 -COM21 -COM22 -COM23
Figure 13 Reference Example for Partial Display
-COM0 -COM1 -COM2 -COM3 -COM4 -COM5 -COM6 -COM7 -COM8 -COM9 -COM10 -COM11 -COM12 -COM13 -COM14 -COM15 -COM16 -COM17 -COM18 -COM19 -COM20 -COM21 -COM22 -COM23
Figure 14 Partial Display (Partial Display Duty=16,initial COM0=0)
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-COM0 -COM1 -COM2 -COM3 -COM4 -COM5 -COM6 -COM7 -COM8 -COM9 -COM10 -COM11 -COM12 -COM13 -COM14 -COM15 -COM16 -COM17 -COM18 -COM19 -COM20 -COM21 -COM22 -COM23
Figure 15 Moving Display (Partial Display Duty=16,Initial COM0=8)
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POWER SUPPLY CIRCUITS
The Power Supply circuits generate the voltage levels necessary to drive liquid crystal driver circuits with low power consumption and the fewest components. There are voltage converter circuits, voltage regulator circuits, and voltage follower circuits. They are controlled by power control instruction. For details, refers to "Instruction Description". Table 4 shows the referenced combinations in using Power Supply circuits. Table 4 Recommended Power Supply Combinations Power Customer Power System Only the internal power supply circuits are used Only the voltage regulator circuits and voltage follower circuits are used Only the voltage follower circuits are used Only the external power supply circuits are used Voltage Converter Circuits These circuits boost up the electric potential between VDD2 and Vss to 3, 4, 5 or 6 times toward positive side and boosted voltage is outputted from VOUT pin. It is possible to select the lower boosting level in any boosting circuit by "Set DC-DC Step-up" instruction. When the higher level is selected by instruction, VOUT voltage is not valid. Note: we would like to recommend to use the external VOUT when the panel is large than 1.8 inch Voltage Regulator Circuits The function of the internal Voltage Regulator circuits is to determine liquid crystal operating voltage, V0, by adjusting resistors, Ra and Rb, within the range of |V0| < |VOUT|. Because VOUT is the operating voltage of operational-amplifier circuits shown in Figure 16, it is necessary to be applied internally or externally. For the Eq. 1, we determine V0 by Ra, Rb and VEV. The Ra and Rb are connected internally or externally by INTRS pin. And VEV called the voltage of electronic volume is determined by Eq. 2, where the parameter Table 5. V0 = (1 + Rb / Ra) x VEV VEV = (1 - (63 - ) / 210) x VREF [V] .................. (Eq. 1) [V] .................. (Eq. 2) is the value selected by instruction, "Set Reference Voltage Register", within the range 0 to 63. VREF voltage at Ta= 25C is shown in Control (VC VR VF) 111 011 001 000 V/C circuits ON OFF OFF OFF V/R circuits ON ON OFF OFF V/F circuits ON ON ON OFF VOUT_IN V0 Without capacitor Without capacitor External input External input V1 to V4 With capacitor With capacitor With capacitor External input
Internal External input OPEN OPEN
Table 5 VREF Voltage at Ta = 25C REF 1 0 Temp. coefficient -0.144% / C External input
VOUT
VREF [ V ] 2.1 VEXT
V0 Rb VEV VR Ra VSS GND
Figure 16 Internal Voltage Regulator Circuit
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In Case of Using Internal Resistors, Ra and Rb (INTRS = "H") When INTRS pin is "H", resistor Ra is connected internally between VR pin and VSS, and Rb is connected between V0 and VR. We determine V0 by two instructions, "Regulator Resistor Select" and "Set Reference Voltage". Table 6 Internal Rb / Ra Ratio depending on 3-bit Data (R2 R1 R0) 3-bit data settings (R2 R1 R0) 000 1 + (Rb / Ra) 2.3 001 3.0 010 3.7 011 4.4 100 5.1 101 5.8 110 6.5 111 7.2
Figure 17 Shows V0 voltage measured by adjusting internal regulator register ratio (Rb / Ra) and 6-bit electronic volume registers for each temperature coefficient at Ta = 25C.
16.000 14.000 12.000 10.000 000 001 010 011 100 101 110 111
8.000 6.000 4.000 2.000 0.000
0
3
6
9
12
15
18
21
24
27
30
33
36
39
42
45
48
51
54
57
60
Figure 17 Electronic Volume Level (Temp. Coefficient = -0.144% / C)
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ST7541
In Case of Using External Resistors, Ra and Rb (INTRS = "L") When INTRS pin is "L", it is necessary to connect external regulator resistor Ra between VR and VSS, and Rb between V0 and VR. Example: For the following requirements 1. LCD driver voltage, V0 = 10V 2. 6-bit reference voltage register = (1, 0, 0, 0, 0, 0) 3. Maximum current flowing Ra, Rb = 1 uA From Eq. 1: 10 = (1 + Rb / Ra) x VEV From Eq. 2: VEV = (1 - (63 - 32) / 210) x 2.1 = 1.79 From Requirement-3: 10 / (Ra + Rb) = 1 From Eq. 3~5: Ra = 1.79 Rb = 8.21 [M] [M] [uA] .................. (Eq. 5) [V] .................. (Eq. 4) [V] .................. (Eq. 3)
Table 7 Shows the Range of V0 depending on the above Requirements. Table 7 The Range of V0 Electronic volume level 0 V0 8.21 ....... ....... 32 10.00 ....... ....... 63 11.73
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Voltage Follower Circuits VLCD voltage (V0) is resistively divided into four voltage levels (V1, V2, V3 and V4), and those output impedance are converted by the Voltage Follower for increasing drive capability. Table 8 shows the relationship between V1 to V4 level and each duty ratio. Table 8 The Relationship between V1 to V4 Level and Each Duty Ratio LCD bias 1/N V1 (N-1)/N x V0 V2 (N-2)/N x V0 V3 2/N x V0 V4 1/N x V0 Remarks N = 5 to 12
Follower Voltage Reference Circuit (Internal Booster & Regulator)
VSS2 VSS C1 VOUT VSS C1
VSS2 VOUT
VDD
INTR
VSS
INTR
Rb V0 VR VSS Ra VSS V0 C2 C2 C2 C2 V1 V2 V3 V4
ST7541
ST7541
VSS VSS V0 C2 C2 C2 C2 V1 V2 V3 V4
Left is using internal Resister Right is using External Resister C1= 1u F ~ 4.7u F , C2 = 0.1u F ~ 1u F (suggestion value: C1=1uF , C2=0.1uF)
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Follower voltage reference circuit (External Vout & Internal Regulator)
External
VOUT
External
VOUT
VDD
INTR
VSS
INTR
Rb V0 VR VSS Ra VSS V0 C2 C2 C2 C2 V1 V2 V3 V4
ST7541
ST7541
VSS VSS V0 C2 C2 C2 C2 V1 V2 V3 V4
Left is using internal Resister Right is using External Resister C1= 1u F ~ 4.7u F , C2 = 0.1u F ~ 1u F (suggestion value: C1=1uF , C2=0.1uF)
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Booster Efficiency By Booster Stages (3X, 4X, 5X, 6X) and Booster Efficiency (Level1~2) commands, we could easily set the best Booster performance with suitable current consumption. If the Booster Efficiency is set to higher level (level2 is higher than level1), The Boost Efficiency is better than lower level, and it just need few more power consumption current. It could be applied to each multiple voltage Condition. When the LCD Panel loading is heavier, then the Performance of Booster will be not in a good working condition. We could set the BE level to be higher. We do not need to change to higher Booster Stage, and just need few more current. The Booster Efficiency Command could be used together with Booster Stage Command to choose one best Boost output condition. We could see the Boost Stage Command as a large scale operation, and see the Booster Efficiency Command as a small scale operation. These commands are very convenient for using.
Level1
Vout Voltage
Level2
5X boost
Loading
VSS Current
Level1
Level2
5X Current
Loading
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RESET CIRCUIT
Setting RST to "L" can initialize internal function. RST pin must connect to the reset pin of MPU and initialization by RST pin is essential before operating. Please note the hardware reset is not same as the software reset. When RST becomes "L", the hardware reset procedure will start. When RESET instruction is executed, the software reset procedure will start. The procedure is listed below: Procedure Oscillator OFF Power Save Mode: P=0 Power Control OFF: VC=0, VR=0, VF=0 Booster Step: DC[1:0]=0 Booster Efficiency: BE=1 Frame Rate: 77Hz, FR[3:0]=0 LCD Bias: 1/12 Bias, BS[2:0]=(1,1,1) Display OFF: D=0, all SEGs/COMs output at VSS Normal Display: REV=0, EON=0 SEG Normal Direction: ADC=0 COM Normal Direction: SHL=0 ICON Control: OFF, ICON=0 Partial Display Duty: L[7:0]=0 N-Line Inversion: OFF, N[4:0]=0 Initial COM0: C[6:0]=0 Initial Display Line: S[6:0]=0 Read-modify-Write: Released Display Data Length (if using 3-Line SPI Interface): D[7:0]=0 FRC/PWM Mode: 4-FRC, 9-PWM Column Address Y[7:1]=0 Page Address P[3:0]=0 V0 Regulator Resistor: R[2:0]=(0,0,0) EV[5:0]=(1,0,0,0,0,0) Gray Scale Setting: [ White Mode ] OFF White Palette: WA[3:0]=0, WB[3:0]=0, WC[3:0]=0, WD[3:0]=0 [ Light Gray Mode ] OFF Light Gray Palette: LA[3:0]=0, LB[3:0]=0, LC[3:0]=0, LD[3:0]=0 [ Dark Gray Mode ] OFF Dark Gray Palette: DA[3:0]=0, DB[3:0]=0, DC[3:0]=0, DD[3:0]=0 [ Black Mode ] OFF Black Palette: BA[3:0]=0, BB[3:0]=0, BC[3:0]=0, BD[3:0]=0 After power-on, RAM data are undefined and the display status is "Display OFF". It's better to initialize whole DDRAM (ex: fill all 00h or write the display pattern) before turning the Display ON. Besides, the power is not stable at the time that the power is just turned ON. A hardware reset is needed to initialize those internal registers after the power is stable. V V Hardware Reset V V V V V V V V V V V V V V V V V V V V V V V Software Reset X X X X X X X X X X X X X X X V V V V V V V V
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COMMAND TABLE
Instruction Mode Set 0 Read display data Write display data Read status ICON control ON/OFF Set page address Set column address MSB Set column address LSB Set Read-modify-Write Reset Read-modify-Write Display ON/OFF 1 1 0 0 0 0 0 0 0 0 0 Set Initial Display Line 0 0 Set Initial COM0 0 Set Partial Display Duty Set N-line Inversion Release N-line Inversion Reverse Display ON/OFF Entire Display ON/OFF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x' 0 L7 0 x' 1 1 1 C6 1 L6 1 x' 1 0 0 C5 0 L5 0 x' 1 1 1 C4 0 L4 0 N4 0 0 0 C3 1 L3 1 N3 0 0 0 C2 0 L2 1 N2 1 1 1 C1 x' L1 x' N1 0 1 0 C0 x' L0 x' N0 0 REV EON 0 0 x' 0 S6 1 S5 0 S4 0 S3 0 S2 1 S1 x' S0 x' 0 1 0 1 0 0 0 0 0 0 0 0 BUSY 1 1 0 0 1 1 1 0 ON 0 0 0 0 1 1 0 1 RES 1 1 0 0 1 1 1 0 FR3 FR2 FR1 FR0 0 BE x' 0 A0 0 R/W 0 DB7 0 DB6 0 DB5 1 DB4 1 DB3 1 DB2 0 DB1 0 DB0 0 Description 2-byte command Set FR (Frame Rate) and BE (Booster Efficiency) Read data into DDRAM Write data into DDRAM MF0 0 P2 Y7 Y3 0 1 1 0 DS1 1 P1 Y6 Y2 0 1 1 x' DS0 ICON P0 Y5 Y1 0 0 D x' Read the internal status ICON=0: ICON disable 0 1 1 0 0 0 0 0 0 P3 0 Y4 0 1 1 0 ICON=1: ICON enable & set page address to 16 Set page address Set column address MSB Set column address LSB DDRAM address control: Read: No change Write: column address +1 Release read-modify-write D=0: Display OFF D=1: Display ON 2-byte command Specify the initial display line to realize vertical scrolling 2-byte command Specify the first COM0 to move display window 2-byte command Set partial display line number 2-byte command Set N-line inversion register Exit N-line inversion mode REV=0: normal display REV=1: reverse display EON=0: normal display EON=1: entire display ON Read data Write data MF2 MF1
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Instruction Power Control Select DC-DC step-up Select Regulator Register Select Electronic Volume Select LCD bias High Power Mode High Power Mode Control A0 0 0 0 0 0 0 0 0 0 0 0 R/W 0 0 0 0 0 0 0 0 0 0 0 DB7 0 0 0 1 x' 0 1 0 1 0 1 DB6 0 1 0 0 x' 1 1 0 1 0 1 DB5 1 1 1 0 EV5 0 1 0 1 0 0 DB4 0 0 0 0 EV4 1 1 1 1 0 0 DB3 1 0 0 0 EV3 0 0 1 0 1 SHL DB2 VC 1 R2 0 EV2 B2 1 0 0 1 x' DB1 VR DC1 R1 0 EV1 B1 1 1 1 0 x' DB0 VF DC0 R0 1 EV0 B0 1 0 1 1 x' Description Set power circuits ON/OFF Select built-in booster step Select the internal resistance ratio of the regulator resistor 2-byte command Adjust contrast level Select LCD bias 2-byte command Enable High Power Mode 2-byte command Controls high driving mode COM bi-directional selection SHL select SHL=0: normal direction SHL=1: reverse direction SEG bi-direction selection ADC select Oscillator ON Set power save mode Release power save mode RESET Set display data length (DDL) 0 0 0 0 0 x' x' 0 0 0 0 0 x' x' 1 1 1 1 1 1 D7 0 0 0 1 1 1 D6 1 1 1 1 1 1 D5 0 0 0 0 0 0 D4 0 1 1 0 0 1 D3 0 0 0 0 0 0 D2 0 1 0 0 1 0 D1 ADC 1 P 1 0 0 D0 ADC=0: normal direction ADC=1: reverse direction Start the built-in oscillator P=0: normal mode P=1: sleep mode Release power save mode Software reset Refer to RESET CIRCUIT 2-byte command Specify the number of data bytes. (3-Line SPI only) FRC: 1=3FRC, 0=4FRC PWM[1:0]: Set FRC/PWM mode 0 0 1 0 0 1 0 FRC PWM1 PWM0 (0,0)=(0,1)=9PWM (1,0)=12PWM (1,1)=15PWM NOP Test Instruction 0 0 0 0 1 1 1 1 1 1 0 1 0 x' 0 x' 1 x' 1 x' No operation Don't use this instruction
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Instruction White palette (1 /2 frame) set PWM pulse width White palette (3rd/4th frame) set PWM pulse width Light palette (1st/2nd frame) set PWM pulse width Light palette (3rd/4th frame) set PWM pulse width Dark palette (1st/2nd frame) set PWM pulse width Dark palette (3rd/4th frame) set PWM pulse width Black palette (1st/2nd frame) set PWM pulse width Black palette (3rd/4th frame) set PWM pulse width
st nd
A0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DB7 1 WB3 1 WD3 1 LB3 1 LD3 1 DB3 1 DD3 1 BB3 1 BD3
DB6 0 WB2 0 WD2 0 LB2 0 LD2 0 DB2 0 DD2 0 BB2 0 BD2
DB5 0 WB1 0 WD1 0 LB1 0 LD1 0 DB1 0 DD1 0 BB1 0 BD1
DB4 0 WB0 0 WD0 0 LB0 0 LD0 0 DB0 0 DD0 0 BB0 0 BD0
DB3 1 WA3 1 WC3 1 LA3 1 LC3 1 DA3 1 DC3 1 BA3 1 BC3
DB2 0 WA2 0 WC2 0 LA2 0 LC2 1 DA2 1 DC2 1 BA2 1 BC2
DB1 0 WA1 0 WC1 1 LA1 1 LC1 0 DA1 0 DC1 1 BA1 1 BC1
DB0 0 WA0 1 WC0 0 LA0 1 LC0 0 DA0 1 DC0 0 BA0 1 BC0
Description Set white mode palette 1st/2nd frame Set white mode palette 3rd/4th frame Set light gray mode palette 1st/2nd frame Set light gray mode palette 3rd/4th frame Set dark gray mode palette 1st/2nd frame Set dark gray mode palette 3rd/4th frame Set black mode palette 1st/2nd frame Set black mode palette 3rd/4th frame
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COMMAND DESCRIPTION
Mode Set 2-byte instruction to set FR (Frame frequency control) and BE (Booster efficiency control) st The 1 Instruction
A0 0 RW 0
nd
DB7 0 DB7
DB6 0 DB6
DB5 1 DB5
DB4 1 DB4
DB3 1 DB3
DB2 0 DB2
DB1 0 DB1
DB0 0 DB0
The 2
A0 0
Instruction
RW 0
FR3
FR2
FR1
FR0
0
BE
x'
0
Frame Rate This command is used to set the frame frequency. FR3 FR2 FR1 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 1 1 0 1 1 1 0 0 1 0 0 1 0 1 1 0 1 1 1 0 1 1 0 1 1 1 1 1 1
FR0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
FR frequency 77 Hz (default) 51 Hz 55 Hz 58 Hz 63 Hz 67 Hz 68 Hz 70 Hz 73 Hz
75 Hz 80 Hz 85 Hz 91 Hz 102 Hz 113 Hz 123 Hz
Booster Efficiency The ST7541 incorporates software configurable Booster Efficiency Command. It could be used with Voltage multiplier to get the suitable Vout and Power consumption. Default setting is Level 2. Flag BE Description 0 1
Booster Efficiency Level 1 Booster Efficiency Level 2
Read Display Data
8-bit data from Display Data RAM specified by the column address and page address can be read by this instruction. As the column address is increased by 1 automatically after each this instruction, the microprocessor can continuously read data from the addressed page. A dummy read is required after loading an address into the column address register. Display Data cannot be read through the serial interface. A0 1 RW 1 DB7 Read data DB6 DB5 DB4 DB3 DB2 DB1 DB0
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Write Display Data
8-bit data of Display Data from the microprocessor can be written to the RAM location specified by the column address and page address. The column address is increased by 1 automatically so that the microprocessor can continuously write data to the addressed page. During auto-increment, the column address wraps to 0 after the last column is written. A0 1 RW 1 DB7 Write data DB6 DB5 DB4 DB3 DB2 DB1 DB0
Set Page Address
Set Page Address
Set Column Address
Set Column Address
Data Write
Dummy Data Read
Column = Column + 1
Column = Column + 1
YES Data Write Continue ?
Data Read
NO Optional Status
Column = Column + 1
YES Data Read Continue ?
NO Optional Status
Figure 18 Sequence for Writing Display Data (Left) and Sequence for Reading Display Data (Right)
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Read Status
Indicates the internal status of the ST7541 A0 0 Flag BUSY D RES RW 1 DB7 BUSY Description The device is busy when internal operation or reset. Any instruction is rejected until BUSY goes Low. 0: chip is active, 1: chip is being busy Indicates display ON / OFF status 0: display OFF, 1: display ON Indicates the initialization is in progress by RST signal or RESET instruction. 0: chip is active, 1: chip is being reset DB6 D DB5 RES DB4 MF2 DB3 MF1 DB2 MF0 DB1 DS1 DB0 DS0
MF DS
Manufacturer ID; recommended value: MF2 MF1 MF0 = [0 0 0] The value of MF2, MF1 and MF0 will follow the hardware selection. Display size ID; recommended value: DS1 DS0 = [0 0] The value of DS1 and DS2 will follow the hardware selection.
ICON Control ON/OFF
This instruction makes ICON enable or disable. By default, ICON display is disabled (ICON= 0). When ICON control register is set to "1", ICON display is enabled and page address is set to "16". Then user can write data for icons. It is impossible to set the page address to "16" by Set Page Address instruction. Therefore, when writing data for icons, ICON control register ON instruction would be used to set the page address to "16". When ICON control register is set to "0", ICON display is disabled. A0 0 RW 0 DB7 1 DB6 0 DB5 1 DB4 0 DB3 0 DB2 0 DB1 1 DB0 ICON
ICON=0: ICON disable (default) ICON=1: ICON enable & set the page address to 16
Set Page Address
Sets the Page Address of display data RAM from the microprocessor into the page address register. Any RAM data bit can be accessed when its Page Address and column address are specified. Along with the column address, the Page Address defines the address of the display RAM to write or read display data. Changing the Page Address doesn't affect the display status. Set Page Address instruction can not be used to set the page address to "16". Use ICON control register ON/OFF instruction to set the page address to "16". A0 0 RW 0 DB7 1 DB6 0 DB5 1 DB4 1 DB3 P3 DB2 P2 DB1 P1 DB0 P0
P3 0 0 : 1 1
P2 0 0 : 1 1
P1 0 0 : 1 1
P0 0 1 : 0 1
Page 0 1 : 14 15
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Set Column Address
Sets the Column Address of display RAM from the microprocessor into the column address register. Along with the Column Address, the Column Address defines the address of the display RAM to write or read display data. When the microprocessor reads or writes display data to or from display RAM, Column Addresses are automatically increased.
Set Column Address MSB
A0 0 RW 0 DB7 0 DB6 0 DB5 0 DB4 1 DB3 0 DB2 Y7 DB1 Y6 DB0 Y5
Set Column Address LSB
A0 0 Y7 0 0 : 1 1 RW 0 Y6 0 0 : 1 1 DB7 0 Y5 0 0 : 1 1 DB6 0 Y4 0 0 : 1 1 DB5 0 Y3 0 0 : 1 1 DB4 0 Y2 0 0 : 1 1 DB3 Y4 Y1 0 1 : 0 1 DB2 Y3 DB1 Y2 DB0 Y1
Column Address 0 1 : 126 127
Set Read-modify-Write
This instruction stops the automatic increment of the column address by the read display data instruction, but the column address is still increased by the write display data instruction. And it reduces the load of microprocessor when the data of a specific area is repeatedly changed during cursor blinking or others. This mode is canceled by the reset Read-modify-Write instruction. A0 0 RW 0 DB7 1 DB6 1 DB5 1 DB4 0 DB3 0 DB2 0 DB1 0 DB0 0
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Reset Read-modify-Write
This instruction releases the Read-modify-Write mode, and makes the column address return to its initial value just before the set Read-modify-Write instruction. A0 0 RW 0 DB7 1 DB6 1 DB5 1 DB4 0 DB3 1 DB2 1 DB1 1 DB0 0
Read-Modify-Write Set Page Address Set Column Address (N) Set Read-modify-Write Dummy Read Data Read Modify Data Data Write (at same Address)
Internal address +1
No
Finished?
Yes
Release Read-modify-Write Internal address return to N Done
Figure 19 Sequence for Read-modify-Write
Display ON / OFF
Turns the display ON or OFF. This command has priority over Entire Display On/Off and Reverse Display On/Off. Commands are accepted while the display is off, but the visual state of the display does not change. A0 0 RW 0 DB7 1 DB6 0 DB5 1 DB4 0 DB3 1 DB2 1 DB1 1 DB0 DON
DON = 1: display ON DON = 0: display OFF
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Set Initial Display Line
Sets the line address of display RAM to determine the initial display line using 2-byte instruction. The RAM display data is displayed at the top of row(COM0) of LCD panel.
The 1 Instruction
A0 0 RW 0
nd
st
DB7 0 DB7 x S4 0 0 0 0 : 1 1 1 1
DB6 1 DB6 S6 S3 0 0 0 0 : 1 1 1 1
DB5 0 DB5 S5 S2 0 0 0 0 : 1 1 1 1
DB4 0 DB4 S4 S1 0 0 1 1 : 0 0 1 1
DB3 0 DB3 S3 S0 0 1 0 1 : 0 1 0 1
DB2 0 DB2 S2
DB1 x DB1 S1 Line address 0 1 2 3 : 124 125 126 127
DB0 x DB0 S0
The 2
A0 0 S6 0 0 0 0 : 1 1 1 1
Instruction
RW 0 S5 0 0 0 0 : 1 1 1 1
S e ttin g In itia l D is p la y L in e S ta rt 1 st I n s tr u c tio n f o r M o d e s e ttin g 2 nd In s tru c tio n fo r In itia l D is p la y L in e s e ttin g S e ttin g In itia l D is p la y L in e E n d
Figure 20 Sequence For Setting Initial Display Line
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Set Initial COM0
Sets the initial row (COM) of the LCD panel using the 2-byte instruction. By using this instruction, it is possible to realize the window moving without the change of display data.
The 1 Instruction
A0 0 RW 0
nd
st
DB7 0 DB7 x C4 0 0 0 0 : 1 1 1 1
DB6 1 DB6 C6 C3 0 0 0 0 : 1 1 1 1
DB5 0 DB5 C5 C2 0 0 0 0 : 1 1 1 1
DB4 0 DB4 C4 C1 0 0 1 1 : 0 0 1 1
DB3 0 DB3 C3 C0 0 1 0 1 : 0 1 0 1
DB2 1 DB2 C2 Initial COM0 COM0 COM1 COM2 COM3 : COM124 COM125 COM126 COM127
DB1 x DB1 C1
DB0 x DB0 C0
The 2
A0 0 C6 0 0 0 0 : 1 1 1 1
Instruction
RW 0 C5 0 0 0 0 : 1 1 1 1
S e tt in g I n itia l C O M 0 S ta r t 1 s t I n s tr u c ti o n f o r M o d e s e tt in g 2 n d I n s t r u c ti o n f o r I n i ti a l C O M 0 s e ttin g S e ttin g I n it ia l C O M 0 E n d
Figure 21 Sequence For Setting Initial COM0
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Set Partial Display Duty
Sets the duty within range of 16 ~ 128 (ICON disabled) or 17 to 129 (ICON enabled) to realize partial display by using the 2-byte instruction.
The 1 Instruction
A0 0 RW 0
nd
st
DB7 0 DB7 L7
DB6 1 DB6 L6
DB5 0 DB5 L5
DB4 0 DB4 L4
DB3 1 DB3 L3
DB2 0 DB2 L2
DB1 x DB1 L1
DB0 x DB0 L0
The 2
A0 0
Instruction
RW 0
D7 0 : 0 0 0 : 0 : 0 1 1 : 1
D6 0 : 0 0 0 : 1 : 1 0 0 : 1
D5 0 : 0 0 0 : 1 : 1 0 0 : 1
D4 0 : 0 1 1 : 0 : 1 0 0 : 1
D3 0 : 1 0 0 : 0 : 1 0 0 : 1
D2 0 : 1 0 0 : 1 : 1 0 0 : 1
D1 0 : 1 0 0 : 0 : 1 0 0 : 1
D0 0 : 1 0 1 : 0 : 1 0 1 : 1
Valid Display Lines (ICON disabled) No operation 16 lines 17 lines : 100 lines : 127 lines 128 lines No Operation
Valid Display Lines (ICON enabled) No operation 16+1 lines 17+1 lines : 100+1 lines : 127+1 lines 128+1 lines No Operation
S e ttin g P a rtia l D is p la y S ta rt 1 s t I n s tr u c tio n fo r M o d e s e ttin g 2 n d I n s tr u c tio n f o r P a rtia l D is p la y D u ty s e ttin g S e ttin g P a rtia l D is p la y E n d
Figure 22 Sequence For Setting Partial Display
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Set N-line Inversion
Sets the inverted line number within range of 3 to 33 to improve the display quality. It controls the phase of the internal LCD frame signal. To get better performance, the display duty (L) should not be complete divide by N-line setting (N). If "L" can be complete divide by "N" (assume K = L / N), the factor (K) should not be even number.
The 1 Instruction
A0 0 RW 0
nd
st
DB7 0 DB7 x N2 0 0 0 0 : 1 1 1
DB6 1 DB6 x N1 0 0 1 1 : 0 1 1
DB5 0 DB5 x N0 0 1 0 1 : 1 0 1
DB4 0 DB4 0
DB3 1 DB3 0
DB2 1 DB2 0
DB1 x DB1 0
DB0 x DB0 0
The 2
A0 0 N4 0 0 0 0 : 1 1 1
Instruction
RW 0 N3 0 0 0 0 : 1 1 1
Selected n-line inversion 0-line inversion (frame inversion) 3-line inversion 4-line inversion 5-line inversion : 31-line inversion 32-line inversion 33-line inversion
Setting N -line Inversion Start 1 st Instruction for M ode setting 2 nd Instruction for N -line Inversion setting Setting N -line Inversion End
Figure 23 Sequence For N-line Inversion
Release N-line Inversion
Returns to the frame inversion condition from the n-line inversion condition. A0 0 RW 0 DB7 1 DB6 1 DB5 1 DB4 0 DB3 0 DB2 1 DB1 0 DB0 0
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Reverse Display ON / OFF
Reverses the display status on LCD panel without rewriting the contents of the display data RAM. A0 0 REV 0 (Normal) 1 (Reverse) RW 0 DB7 1 DB6 0 DB5 1 DB4 0 DB3 0 DB2 1 DB1 1 DB0 REV
DDRAM data = "00" White ("00") Black ("11")
DDRAM data = "01" Light gray ("01") Dark gray ("10")
DDRAM data = "10" Dark gray ("10") Light gray ("01")
DDRAM data = "11" Black ("11") White ("00")
Entire Display ON / OFF
Forces the whole LCD points to be turned on regardless of the contents of the display data RAM. At this time, the contents of the display data RAM are held. This instruction has priority over the Reverse Display ON / OFF instruction. A0 0 EON 0 (Normal) 1 (Entire) RW 0 DB7 1 DB6 0 DB5 1 DB4 0 DB3 0 DB2 1 DB1 0 DB0 EON
DDRAM data = "00" White ("00") Black ("11")
DDRAM data = "01" Light gray ("01") Black ("11")
DDRAM data = "10" Dark gray ("10") Black ("11")
DDRAM data = "11" Black ("11") Black ("11")
Power Control
Selects one of eight power circuit functions by using 3-bit register. An external power supply and part of internal power supply functions can be used simultaneously. A0 0 VC 0 1 - - RW 0 VR - 0 1 - DB7 0 VF - - 0 1 DB6 0 DB5 1 DB4 0 DB3 1 DB2 VC DB1 VR DB0 VF
Status of internal power supply circuits Internal voltage converter circuit is OFF Internal voltage converter circuit is ON Internal voltage regulator circuit is OFF Internal voltage regulator circuit is ON Internal voltage follower circuit is OFF Internal voltage follower circuit is ON
Select DC-DC Step-up
Selects one of 4 DC-DC step-up to reduce the power consumption by this instruction. It is very useful to realize the partial display function. A0 0 DC1 0 0 1 1 RW 0 DB7 0 DC0 0 1 0 1 DB6 1 DB5 1 DB4 0 DB3 0 DB2 1 DB1 DC1 DB0 DC0
Selected DC-DC converter circuit 3 times boosting circuit 4 times boosting circuit 5 times boosting circuit 6 times boosting circuit
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Select Regulator Resistor
Selects resistance ratio of the internal resistor used in the internal voltage regulator. See voltage regulator section in power supply circuit. A0 0 R2 0 0 0 0 1 1 1 1 RW 0 DB7 0 DB6 0 R1 0 0 1 1 0 0 1 1 DB5 1 DB4 0 R0 0 1 0 1 0 1 0 1 DB3 0 DB2 R2 DB1 R1 1+ (Rb / Ra) 2.3 3.0 3.7 4.4 5.1 5.8 6.5 7.2 DB0 R0
Set Electronic Volume
Consist of 2-byte Instructions. The 1st instruction set Reference Voltage mode, the 2nd one updates the contents of reference voltage register. After second instruction, Reference Voltage mode is released.
The 1 Instruction: Set Reference Voltage Select Mode
A0 0 RW 0
nd
st
DB7 1 DB7 x EV3 0 0 : : 1 1 EV2 0 0 : : 1 1
DB6 0 DB6 x EV1 0 0 : : 1 1
DB5 0 DB5 EV5 EV0 0 1 : : 0 1
DB4 0 DB4 EV4
DB3 0 DB3 EV3
DB2 0 DB2 EV2
DB1 0 DB1 EV1
DB0 1 DB0 EV0
The 2
A0 0 EV5 0 0 : : 1 1
Instruction: Set Reference Voltage Register
RW 0 EV4 0 0 : : 1 1
Reference voltage parameter (a) 0 1 : : 62 63
High Power Mode Enable This 2-byte Instruction enables the high power mode. The high power mode control command is valid after this
2-byte Instruction.
The 1 Instruction
A0 0 RW 0
nd
st
DB7 1 DB7
DB6 1 DB6
DB5 1 DB5
DB4 1 DB4
DB3 0 DB3
DB2 1 DB2
DB1 1 DB1
DB0 1 DB0
The 2
A0 0
Instruction
RW 0
0
0
0
1
1
0
1
0
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High Power Mode Control This double command controls the high power mode. The driving strength is enhanced and the current consumption will be larger. st The 1 Instruction
A0 0 RW 0
nd
DB7 1 DB7
DB6 1 DB6
DB5 1 DB5
DB4 1 DB4
DB3 0 DB3
DB2 0 DB2
DB1 1 DB1
DB0 1 DB0
The 2
A0 0
Instruction
RW 0
0
0
0
0
1
1
0
1
Select LCD Bias
Selects LCD bias ratio of the voltage required for driving the LCD. A0 0 B2 0 0 0 0 1 1 1 1 RW 0 DB7 0 B1 0 0 1 1 0 0 1 1 DB6 1 DB5 0 B0 0 1 0 1 0 1 0 1 DB4 1 DB3 0 DB2 B2 DB1 B1 DB0 B0
LCD bias 1/5 1/6 1/7 1/8 1/9 1/10 1/11 1/12
SHL Select
COM output scanning direction is selected by this instruction which determines the LCD driver output status. A0 0 RW 0 DB7 1 DB6 1 DB5 0 DB4 0 DB3 SHL DB2 x DB1 x DB0 x
SHL = 0: normal direction (COM0 COM127) SHL = 1: reverse direction (COM127 COM0)
ADC Select
Changes the relationship between RAM column address and segment driver. The direction of segment driver output pins could be reversed by software. This makes IC layout flexible in LCD module assembly. A0 0 RW 0 DB7 1 DB6 0 DB5 1 DB4 0 DB3 0 DB2 0 DB1 0 DB0 ADC
ADC = 0: normal direction (SEG0 SEG127) ADC = 1: reverse direction (SEG127 SEG0)
Oscillator ON
This instruction enables the built-in oscillator circuit. A0 0 RW 0 DB7 1 DB6 0 DB5 1 DB4 0 DB3 1 DB2 0 DB1 1 DB0 1
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Power Save
The ST7541 enters the Power Save status to reduce the power consumption to the static power consumption value and returns to the normal operation status by the following instructions.
Set Power Save Mode
A0 0 RW 0 DB7 1 DB6 0 DB5 1 DB4 0 DB3 1 DB2 0 DB1 0 DB0 P
P = 0: normal mode , P = 1: sleep mode
Release Power Save Mode
A0 0 RW 0 DB7 1 DB6 1 DB5 1 DB4 0 DB3 0 DB2 0 DB1 0 DB0 1
Set Power Save Mode (Sleep Mode)
Sleep Mode Oscillator Circuit: OFF LCD Power Supply Circuit: OFF All COM / SEG Output Level: VSS Consumption Current < 2uA
Release Power Save Mode (Sleep Mode)
Figure 24 Power Save Routine
RESET
RESET instruction initial display line, column address, page address, and common output status select to their initial status, but dose not affect the contents of display data RAM. This instruction cannot initialize the LCD power supply, which is initialized by the RST pin. A0 0 RW 0 DB7 1 DB6 1 DB5 1 DB4 0 DB3 0 DB2 0 DB1 1 DB0 0
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Set Display Data Length (3-Line SPI Mode)
Consists of 2 bytes instruction. This command is used in 3-Line SPI mode only(PS0 = "L" and PS1 = "L" ). It will be two continuous commands, the first byte control the data direction(write mode only) and inform the LCD driver the second byte will be number of data bytes will be write. When A0 is not used, the Display Data Length instruction is used to indicate that a specified number of display data bytes are to be transmitted. The next byte after the display data string is handled as command data.
The 1 Instruction: Set Data Direction (Only Write Mode)
A0 X RW x
nd
st
DB7 1 DB7 D7 D4 0 0 0 : 1 1 1 D3 0 0 0 : 1 1 1
DB6 1 DB6 D6 D2 0 0 0 : 1 1 1
DB5 1 DB5 D5 D1 0 0 1 : 0 1 1 D0 0 1 0 : 1 0 1
DB4 0 DB4 D4
DB3 1 DB3 D3
DB2 0 DB2 D2
DB1 0 DB1 D1
DB0 0 DB0 D0
The 2
A0 x D7 0 0 0 : 1 1 1
Instruction: Set Display Data Length (DDL) Register
RW x
D6 0 0 0 : 1 1 1
D5 0 0 0 : 1 1 1
Display Data Length 1 2 3 : 254 255 256
Set PWM & FRC mode
Selects 3/4 FRC and 9 / 12 / 15 PWM A0 0 FRC 0 1 - RW 0 DB7 1 DB6 0 PWM1 - 0 1 1 DB5 0 DB4 1 DB3 0 PWM0 - 0 or 1 0 1 DB2 FRC DB1 PWM1 DB0 PWM0
Status of PWM & FRC 4FRC 3FRC 9PWM 12PWM 15PWM
NOP
No operation A0 0 RW 0 DB7 1 DB6 1 DB5 1 DB4 0 DB3 0 DB2 0 DB1 1 DB0 1
Test Instruction
This instruction is for testing IC. Please do not use it. A0 0 RW 0 DB7 1 DB6 1 DB5 1 DB4 1 DB3 x DB2 x DB1 x DB0 x
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Set Gray Scale Mode & Register
Consists of 2 bytes instruction. The first byte sets grayscale mode and the second byte updates the contents of gray scale register without issuing any other instruction.
- Set Gray Scale Mode
A0 0 GM2 0 0 0 0 1 1 1 1 RW 0 GM1 0 0 1 1 0 0 1 1 DB7 1 GM0 0 1 0 1 0 1 0 1 DB6 0 DB5 0 DB4 0 DB3 1 DB2 GM2 DB1 GM1 DB0 GM0
Description st nd In case of setting whit mode and 1 / 2 frame rd th In case of setting whit mode and 3 / 4 frame st nd In case of setting light gray mode and 1 / 2 frame rd th In case of setting light gray mode and 3 / 4 frame st nd In case of setting dark gray mode and 1 / 2 frame rd th In case of setting dark gray mode and 3 / 4 frame st nd In case of setting black mode and 1 / 2 frame rd th In case of setting black mode and 3 / 4 frame
--Set Gray Scale Register
A0 0 0 RW 0 0 DB7 GB3 GD3 DB6 GB2 GD2 DB5 GB1 GD1 DB4 GB0 GD0 DB3 GA3 GC3 DB2 GA2 GC2 DB1 GA1 GC1 DB0 GA0 GC0
Pulse width Pulse width Pulse width GA3, GB3, GA2, GB2, GA1, GB1, GA0, GB0, GC3, GD3 GC2, GD2 GC1, GD1 GC0, GD0 (9 PWM) (12 PWM) (15 PWM) 0 0 0 0 0/9 0/12 0/15 0 0 0 1 1/9 1/12 1/15 : : : : : : : 1 0 0 1 9/9 9/12 9/15 1 0 1 0 0/9 10/12 10/15 1 0 1 0 0/9 11/12 11/15 1 1 0 0 0/9 12/12 12/15 1 1 0 1 0/9 0/12 13/15 1 1 1 0 0/9 0/12 14/15 1 1 1 1 0/9 0/12 15/15 * GA3=WA3, LA3, DA3, BA3 GA2=WA2, LA2, DA2, BA2 GA1=WA1, LA1, DA1, BA1 GA0=WA0, LA0, DA0, BA0 GB3=WB3, LB3, DB3, BB3 GA2=WB2, LB2, DB2, BB2 GA1=WB1, LB1, DB1, BB1 GA0=WB0, LB0, DB0, BB0 GC3=WC3, LC3, DC3, BC3 GA2=WC2, LC2, DC2, BC2 GA1=WC1, LC1, DC1, BC1 GA0=WC0, LC0, DC0, BC0 GD3=WD3, LD3, DD3, BD3 GA2=WD2, LD2, DD2, BD2 GA1=WD1, LD1, DD1, BD1 GA0=WD0, LD0, DD0, BD0
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COMMAND DESCRIPTION
Referential Instruction Setup Flow: Initializing with the built-in Power Supply Circuits
Figure 25 Initializing with the Built-in Power Supply Circuits
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Referential Instruction Setup Flow: Initializing without the built-in Power Supply Circuits
User System Setup by External Pins Start of Initialization
Power ON(VDD-VSS) Keeping the RST Pin="L"
Waiting for Stabilizing the Power
RST Pin="H"
Set Power Save
User Application Setup by Internal Instructions [Display Duty Select] [ADC Select] [SHL Select] [COM0 Register Select] User LCD Power Setup by Internal Instructions [Oscillator ON] [Regulator Resistor] [Electronic Volume Register Select] [LCD Bias Register Select]
[Power Control VC,VR,VF=0,0,0]
Release Power Save Waiting for Stabilizing the LCD Power Levels
End of Initialization
Figure 26 Initializing without Built-in Power Supply Circuits
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Referential Instruction Setup Flow: Data Displaying
End of Initialization
Display Data RAM Addressing by Instruction [Initial Display Line] [Set Page Address] [Set Column Address]
Write Display Data by Instruction [Display Data Write]
Turn Display ON/OFF Instruction [Display ON/OFF]
End of Data Display
Figure 27 Data Displaying
Referential Instruction Setup Flow: Power OFF Optional Status
Set Power Save by Instruction
Power OFF(VDD-VSS)
End of Power OFF
Figure 28 Power OFF
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LIMITING VALUES
In accordance with the Absolutely Maximum Rating System, please refer to note 1 and 2. Parameter Power Supply Voltage Power supply voltage Power supply voltage Power supply voltage Power supply voltage Input voltage Output voltage Operating temperature Storage temperature Symbol VDD VDD2 V0 VOUT_IN V1, V2, V3, V4 VIN VO TOPR TSTR Conditions -0.3 ~ +3.6 1.7 ~ 3.3 3.5 ~ 15 -0.5 ~ +20 0.3 to VOUT_IN -0.5 to VDD+0.5 -0.5 to VDD+0.5 -30 to +85 -65 to +150 Unit V V V V V V V C C
VLCD
V1 to V4
VDD
VDD
VSS System (MPU) side
VSS ST7541 chip side
VSS
Note: 1. 2. 3. Stresses above those listed under Limiting Values may cause permanent damage to the device. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted. Insure that the voltage levels of V1, V2, V3, and V4 are always such that VOUT_IN V0 V1 V2 V3 V4 Vss
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ST7541
DC CHARACTERISTICS
VDD = 1.8 V to 3.3V; VSS = 0 V; VLCD = 3.5 to 15.0V; Tamb=-30~+85C; unless otherwise specified. Item Operating Voltage (1) Operating Voltage (2) High-level Input Voltage Low-level Input Voltage High-level Output Voltage Low-level Output Voltage Input leakage current Output leakage current Liquid Crystal Driver ON Resistance Internal Oscillator Frequency Oscillator External Input Frame Rate Symbol VDD VDD2 VIHC VILC VOHC VOLC ILI ILO VIN = VDD or VSS VIN = VDD or VSS VOUT_IN RON Ta = 25C = 15.0 V VOUT_IN = 8.0 V fOSC fCL fFRAME 1/128 duty Ta = 25C 9 PWM -- -- 88.7 77 Rating Min. -- -- Typ. -- -- Max. 15 15 92.5 85 kHz Hz OSC Condition Rating Min. 1.8 2.4 0.7 x VDD VSS 0.7 x VDD VSS -1.0 -3.0 -- -- -- Typ. -- -- -- -- -- -- -- -- 2.0 3.2 443.5 Max. 3.3 3.3 VDD 0.3 x VDD VDD 0.3 x VDD 1.0 3.0 3.5 K 5.4 462.5 kHz Units V V V V V V A A Applicabl e Pin VDD*1 VDD2 *2 *2 *3 *3 *4 *5 SEGn COMn *6
*7
Item Step-up Circuit output voltage Voltage regulator operating Voltage
Symbol VOUT_OUT VOUT_IN
Condition
Units V V
Applicable Pin VOUT_OUT VOUT_IN
Ver 1.9
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2007/9/3
ST7541
Bare Dice Consumption Current : During Display, with the Internal Power Supply, Current consumed by total ICs when an external power supply(VDD,VDD2) is used . Test pattern Symbol Condition VDD = 3.3 V, Display Pattern SNOW ISS V0 - VSS = 10.7 V 5X booster 1/11 bias Power Down ISS Ta = 25C -- 0.01 2 A *9 -- 550 650 A *8 Rating Min. Typ. Max. Units Notes
Notes to the DC characteristics 1. The maximum possible VOUT voltage that may be generated is dependent on voltage, temperature and (display) load. 2. Internal clock 3. Power-down mode. During power down all static currents are switched off. 4. If external VLCD, the display load current is not transmitted to IDD. 5. VOUT external voltage applied to VOUT_IN pin; VOUT_IN disconnected from VOUT_OUT References for items market with * *1 While a broad range of operating voltages is guaranteed, performance cannot be guaranteed if there are sudden fluctuations to the voltage while the MPU is being accessed. *2 The A0, D0 to D5, D6 (SI), D7 (SCL), /RD (E), /WR ,/(R/W), CSB, IMS, OSC, P/S, /DOF, RST ,and MODE terminals. *3 The D0 to D7, and OSC terminals. *4 The A0,/RD (E), /WR ,/(R/W), CSB, IMS, OSC, P/S, /DOF, RST ,and MODE terminals. *5 Applies when the D0 to D5, D6 (SI), D7 (SCL) terminals are in a high impedance state. *6 These are the resistance values for when a 0.1 V voltage is applied between the output terminal SEGn or COMn and the various power supply terminals (V1, V2, V3, and V4). These are specified for the operating voltage range. RON = 0.1 V /I (Where I is the current that flows when 0.1 V is applied while the power supply is ON.) *7 The relationship between the oscillator frequency and the frame rate frequency. *8,9 It indicates the current consumed on IC alone when the internal oscillator circuit and display are turned on.
Ver 1.9
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2007/9/3
ST7541
TIMING CHARACTERISTICS
System Bus Read/Write Characteristics (For the 8080 Series MPU)
Figure 29
(VDD = 3.3V, Ta=-30~85C) Item Address hold time Address setup time System cycle time Write L pulse width Write H pulse width Read L pulse width Read H pulse width Data setup time (Write) Write Data hold time (Write) Data access time (Read) Output disable time (Read) D0 to D7 /WR A0 Signal Symbol tAH8 tAW8 tCYC8 tCCLW tCCHW tCCLR tCCHR tDS8 tDH8 tACC8 tOH8 CL = 100 pF CL = 100 pF Condition Rating Min. 0 0 240 80 80 140 80 40 10 -- 5 -- -- 70 50 Max. -- -- -- -- -- -- ns Units
/RD
Ver 1.9
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(VDD = 2.7V, Ta=-30~85C) Item Address hold time Address setup time System cycle time Write L pulse width Write H pulse width Read L pulse width Read H pulse width Data setup time (Write) Write Data hold time (Write) Data access time (Read) Output disable time (Read) D0 to D7 /WR A0 Signal Symbol tAH8 tAW8 tCYC8 tCCLW tCCHW tCCLR tCCHR tDS8 tDH8 tACC8 tOH8 CL = 100 pF CL = 100 pF Condition Rating Min. 0 0 400 220 180 220 180 40 15 -- 10 Max. -- -- -- -- -- -- -- -- -- 140 100 ns Units
/RD
(VDD = 1.8V, Ta=-30~85C) Item Address hold time Address setup time System cycle time Write L pulse width Write H pulse width Read L pulse width Read H pulse width Data setup time (Write) Write Data hold time (Write) Data access time (Read) Output disable time (Read) D0 to D7 /WR A0 Signal Symbol tAH8 tAW8 tCYC8 tCCLW tCCHW tCCLR tCCHR tDS8 tDH8 tACC8 tOH8 CL = 100 pF CL = 100 pF Condition Rating Min. 0 0 640 360 280 360 280 80 30 -- 10 -- -- 240 200 Max. -- -- -- -- -- -- ns Units
/RD
*1 The input signal rise time and fall time (tr, tf) is specified at 15 ns or less. When the system cycle time is extremely fast, (tr +tf) (tCYC8 - tCCLW - tCCHW) for (tr + tf) (tCYC8 - tCCLR - tCCHR) are specified. *2 All timing is specified using 20% and 80% of VDD as the reference. *3 tCCLW and tCCLR are specified as the overlap between CSB being "L" and WR and RD being at the "L" level.
Ver 1.9
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ST7541
System Bus Read/Write Characteristics (For the 6800 Series MPU)
Figure 30
(VDD = 3.3 V, Ta=-30~85C) Item Address hold time Address setup time System cycle time Enable L pulse width (WRITE) Enable H pulse width (WRITE) Enable L pulse width (READ) Enable H pulse width (READ) WRITE Data setup time WRITE Data hold time READ access time READ Output disable time D0 to D7 E A0, R/W Signal Symbol tAH6 tAW6 tCYC6 tEWLW tEWHW tEWLR tEWHR tDS6 tDH6 tACC6 tOH6 CL = 100 pF CL = 100 pF Condition Rating Min. 0 0 240 80 80 80 140 40 10 -- 5 -- -- 70 50 Max. -- -- -- -- -- -- ns Units
Ver 1.9
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(VDD = 2.7V, Ta=-30~85C) Item Address hold time Address setup time System cycle time Enable L pulse width (WRITE) Enable H pulse width (WRITE) Enable L pulse width (READ) Enable H pulse width (READ) WRITE Data setup time WRITE Data hold time READ access time READ Output disable time D0 to D7 E A0, R/W Signal Symbol tAH6 tAW6 tCYC6 tEWLW tEWHW tEWLR tEWHR tDS6 tDH6 tACC6 tOH6 CL = 100 pF CL = 100 pF Condition Rating Min. 0 0 400 220 180 220 180 40 15 -- 10 Max. -- -- -- -- -- -- -- -- -- 140 100 ns Units
(VDD =1.8V, Ta=-30~85C) Item Address hold time Address setup time System cycle time Enable L pulse width (WRITE) Enable H pulse width (WRITE) Enable L pulse width (READ) Enable H pulse width (READ) WRITE Data setup time WRITE Data hold time READ access time READ Output disable time D0 to D7 E A0, R/W Signal Symbol tAH6 tAW6 tCYC6 tEWLW tEWHW tEWLR tEWHR tDS6 tDH6 tACC6 tOH6 CL = 100 pF CL = 100 pF Condition Rating Min. 0 0 640 360 280 360 280 80 30 -- 10 Max. -- -- -- -- -- -- -- -- -- 240 200 ns Units
*1 The input signal rise time and fall time (tr, tf) is specified at 15 ns or less. When the system cycle time is extremely fast, (tr +tf) (tCYC6 - tEWLW - tEWHW) for (tr + tf) (tCYC6 - tEWLR - tEWHR) are specified. *2 All timing is specified using 20% and 80% of VDD as the reference. *3 tEWLW and tEWLR are specified as the overlap between CSB being "L" and E.
Ver 1.9
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ST7541
Serial Interface (4-Line Interface)
First bit
Figure 31
Last bit
(VDD=3.3V, Ta=-30~85C) Item Serial Clock Period SCL "H" pulse width SCL "L" pulse width Address setup time Address hold time Data setup time Data hold time CS-SCL time CS-SCL time A0 SI CSB SCL Signal Symbol tSCYC tSHW tSLW tSAS tSAH tSDS tSDH tCSS tCSH Condition Rating Min. 50 25 25 20 10 20 10 20 40 Rating Min. 100 50 50 30 20 30 20 30 60 Max. -- -- -- -- -- -- -- -- -- ns Max. -- -- -- -- -- -- -- -- -- ns Units
(VDD=2.7V, Ta=-30~85C) Item Serial Clock Period SCL "H" pulse width SCL "L" pulse width Address setup time Address hold time Data setup time Data hold time CS-SCL time CS-SCL time A0 SI CSB SCL Signal Symbol tSCYC tSHW tSLW tSAS tSAH tSDS tSDH tCSS tCSH Condition Units
Ver 1.9
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(VDD=1.8V, Ta=-30~85C) Item Serial Clock Period SCL "H" pulse width SCL "L" pulse width Address setup time Address hold time Data setup time Data hold time CS-SCL time CS-SCL time A0 SI CSB SCL Signal Symbol tSCYC tSHW tSLW tSAS tSAH tSDS tSDH tCSS tCSH Condition Rating Min. 200 80 80 60 30 60 30 40 100 Max. -- -- -- -- -- -- -- -- -- ns Units
*1 The input signal rise and fall time (tr, tf) are specified at 15 ns or less. *2 All timing is specified using 20% and 80% of VDD as the standard.
Ver 1.9
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2007/9/3
ST7541
Serial Interface (3-Line Interface)
First bit
Figure 32
Last bit
(VDD=3.3V, Ta=-30~85C) Item Serial Clock Period SCL "H" pulse width SCL "L" pulse width Data setup time Data hold time CS-SCL time CS-SCL time SI CSB SCL Signal Symbol tSCYC tSHW tSLW tSDS tSDH tCSS tCSH Condition Rating Min. 50 25 25 20 10 20 40 Rating Min. 100 50 50 30 20 30 60 Rating Min. 200 80 80 60 30 40 100 Max. -- -- -- -- -- -- -- ns Max. -- -- -- -- -- -- -- ns Max. -- -- -- -- -- -- -- ns Units
(VDD=2.7V, Ta=-30~85C) Item Serial Clock Period SCL "H" pulse width SCL "L" pulse width Data setup time Data hold time CS-SCL time CS-SCL time SI CSB SCL Signal Symbol tSCYC tSHW tSLW tSDS tSDH tCSS tCSH Condition Units
(VDD=1.8V, Ta=-30~85C) Item Serial Clock Period SCL "H" pulse width SCL "L" pulse width Data setup time Data hold time CS-SCL time CS-SCL time SI CSB SCL Signal Symbol tSCYC tSHW tSLW tSDS tSDH tCSS tCSH Condition Units
*1 The input signal rise and fall time (tr, tf) are specified at 15 ns or less. *2 All timing is specified using 20% and 80% of VDD as the standard.
Ver 1.9
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ST7541
Serial Interface (IIC Interface)
(VDD=3.3V, Ta=-30~85C) Item SCL clock frequency SCL clock low period SCL clock high period Data set-up time Data hold time SCL,SDA rise time SCL,SDA fall time Capacitive load represented by each bus line Setup time for a repeated START condition Start condition hold time Setup time for STOP ondition Tolerable spike width on bus BUS free time between a STOP and StART condition SCL SI SI Signal Symbol SCL SCL SCL SI SI SCL SCL FSCLK TLOW THIGH TSU;Data THD;Data TR TF Cb TSU;SUA THD;STA TSU;STO TSW TBUF Condition 1.3 0.6 100 0 Rating Min. 0.9 Max. 400 Units kHZ us us ns us ns ns pF us us us ns us
20+0.1Cb 300 20+0.1Cb 300 0.6 0.6 0.6 1.3 400 50
Ver 1.9
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ST7541
RESET TIMING
tRW
RST
tR
Internal Status
During Reset ...
Figure 33
Reset Finished
(VDD = 3.3V, Ta=-30~85C) Item Reset time Reset "L" pulse width RST Signal Symbol tR tRW Condition Rating Min. -- 1 Typ. -- -- Rating Min. -- 1.5 Typ. -- -- Rating Min. -- 2.0 Typ. -- -- Max. 2.0 -- Max. 1.5 -- Max. 1 -- Units us us
(VDD = 2.7V, Ta=-30~85C) Item Reset time Reset "L" pulse width RST Signal Symbol tR tRW Condition Units us us
(VDD = 1.8V, Ta=-30~85C) Item Reset time Reset "L" pulse width RST Signal Symbol tR tRW Condition Units us us
Ver 1.9
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2007/9/3
ST7541
POWER PAD CONNECT
The pinning of the ST7541 is optimized for single plane wiring e.g. for chip-on-glass display modules. Display size: 129 X 128 pixels.
Display 129 X 128 pixels
COM
SEG
COM
ST7541 VDD2 VDD VSS1 VSS2
*6 if external oscillator 5
Cvout I/O VDD CVDD VSS
Figure 34 Application diagram: internal charge pump is used and s single VDD
Display 129 X 128 pixels
COM
SEG
VOUT_OUT VOUT_IN
COM
ST7541 VDD2 VDD VSS1 VSS2
*6 if external oscillator 5
VDD1 CVDD1 Cvout I/O VDD2 CVDD2 VSS
Figure 35 Application diagram: Internal charge pump is used and two separate VDD(VDD2)
Ver 1.9
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VOUT_OUY VOUT_IN
2007/9/3
ST7541
Display 129 X 128 pixels
COM
SEG
COM
ST7541 VDD2 VDD1 VSS1 VSS2
*6 if external oscillator 5
I/O VDD2 CVDD VSS
Figure 36 application diagram: External high voltage generation is used
The required minimum value for the external capacitors in an application with the ST7541 are: CVLCD = min. 100nF min. 1.0 F Higher capacitor values are recommended for ripple reduction.
VOUT_OUT VOUT_IN
VL2
CVDD,2=
Ver 1.9
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2007/9/3
ST7541
THE MPU INTERFACE (REFERENCE EXAMPLES)
The ST7541 Series can be connected to either60X86 Series MPUs or to 6800Swries MPUs. Moreover, using the serial interface it is possible to operate the ST7541 series chips with fewer signal lines. The display area can be enlarged by using multiple ST7541 Series chips. When this is done, the chip select signal can be used to select the individual Ics to access. (1) 8080 Series MPUs
VDD VCC A0 CS1 MPU DO to D7 RD WR RES RESET A0 CSB D0 to D7 E (/RD) R/W (/WR) /RES VSS VSS ST7541 VDD
GND
(2) 6800 Series MPUs
VDD VCC A0 CS1 MPU DO to D7 E R/W RES RESET A0 CSB D0 to D7 /RD (E) /W R (R/W ) /RES VSS VSS ST7541 PS
V DD VCC A0 CS1 MPU A0 ST7541 V SS V SS C SB V DD
VDD IM S
GND
(3) Using the Serial Interface (4-line interface)
P ort 1 P ort 2 R ES GND R E SET
SI SC L /R E S
Ver 1.9
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(4) Using the Serial Interface (3-line interface)
VDD VCC VDD
Port 1 Port 2 RES GND RESET
SI SCL /RES VSS VSS
(5) Using the Serial Interface (IIC interface)
VDD VCC R MPU R ST7541 VSS VSS VDD
Port 1 Port 2 RES RESET
SDA SCL /RES
GND
Ver 1.9
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ST7541
CS1 MPU
CSB
2007/9/3
ST7541
APPLICATION Program Example
4-Gray programming example for ST7541 SETP 0 1 Start A0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 2 3.a 3.b 0 0 0 0 0 3.d 4.a 4.b 0 0 0 1 0 0 1 x' 0 0 0 0 1 0 0 x' 1 1 0 1 1 1 0 Ev5 0 1 0 0 0 0 0 Ev4 1 0 1 0 1 0 0 0 0 1 0 1 R2 0 Ev3 B2 0 x' 1 0 0 1 Set DC-DC Step up Set Vout Set Ra/Rb Set R[2:0] Set EV Set Ev[5:0] Ev0 Set Bias Set B[2:0] Gray-Scale Setting Mode Set. 0 x' 1 0 0 SET Power Control Booster ON Regulator ON Follower ON 5.b 6 A0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 1 1 7 1 0 0 0 0 0 1 1 1 0 0 0 1 0 0 1 1 1 1 1 1 1 0 0 A0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Display control. Display on Data Write. Y,X are initialized to 0 by default, so they aren't set here... A0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 1 0 0 1 1 0 0 0 0 1 1 0 0 0 0 1 1 Data Write. 1 SERIAL BUS BYTE DISPLAY OPERATION CSB IS going low. Mode Set. FR[3:0] = 0000 BE= 1 OSC ON
A0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 A0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DC1 DC0 R1 0 Ev2 B1 R0 1 Ev1 B0 A0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
3.c A0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
A0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 SET pulse width of Gray scale A0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 0 1 0 1 1 0 0 1 0 1 0 1 1
5.a
A0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0
8
A0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 1 0 0 1 1 0 0 0 0 1 1 0 0 0 0 1 1
Data Write.
9
A0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 1 0 0 1 1 0 0 0 0 1 1 0 0 0 0 1 1
Data Write.
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10 A0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 Data Write.
11
A0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Data Write.
12
A0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 1
Data Write.
13
A0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Data Write.
14
A0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 1
Data Write.
15
A0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 1 0 1 0 0 1 1 1
Display Control. Set Reverse display mode REV=1
16
A0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0
Set column address of RAM. Set address to "00000000". Y[7:0]=00000000 (Y0 default is 0)
17
A0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Data Write.
Ver 1.9
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programming example for ST7541(Use IIC Interface) SETP 1 2 3 4 SERIAL BUS BYTE IIC INTERFACE Start DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 5 6.a 6.b 6.c 1 0 0 1 x' 6.d 7.a 7.b 0 0 0 0 0 1 0 0 x' 1 0 1 0 1 1 1 0 Ev5 0 0 1 0 0 0 0 0 Ev4 1 0 0 1 1 1 0 0 0 0 0 0 0 1 0 0 x' 1 0 0 0 1 Set DC-DC Step up Set Vout Set Ra/Rb Set R[2:0] Set EV Set Ev[5:0] Ev0 Set Bias Set B[2:0] Gray-Scale Setting Mode Set. 0 x' 1 0 0 SET Power Control Booster ON Regulator ON Follower ON 8.b 9 10 11 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 0 1 0 1 1 1 1 IIC INTERFACE Start DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 1 0 0 0 1 1 0 0 0 0 0 0 0 1 1 0 1 1 0 0 0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 12 Display control. Display on restart Slave address for write Control byte with clear Co bit and A0 set to logic 1 Data Write. Y,X are initialized to 0 by default, so they aren't set here... DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 13 0 1 1 0 0 0 0 1 1 0 0 0 0 1 1 Data Write. 1 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Slave address for write Control byte with cleared Co bit and A0 set to logic 0 Mode Set. FR[3:0] = 0000 BE= 1 OSC ON DISPLAY OPERATION
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DC1 DC0 R0 1 Ev1 B0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 R2 R1 0 Ev3 B2 0 Ev2 B1 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 SET pulse width of Gray scale DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 1 0 1 1 0 0 1 0 1 0 1 1
8.a
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0
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DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 14 0 1 1 0 0 0 0 1 1 0 0 0 0 1 1 Data Write.
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 15 0 1 1 0 0 0 0 1 1 0 0 0 0 1 1
Data Write.
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 16 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0
Data Write.
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 17 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Data Write.
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 18 0 1 1 0 0 0 0 0 0 0 0 0 0 1 1
Data Write.
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 19 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Data Write.
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 20 0 1 1 0 0 0 0 0 0 0 0 0 0 1 1
Data Write.
21 22 23
IIC INTERFACE start DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 1 0 0 0 1 0 0 0 0 0 1 0 1 0 1 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
restart Slave address for write Control byte with set Co bit and A0 set to logic 0 Display Control. Set Reverse display mode REV=1
24
25
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 0 0 0 0 0 0 0
Control byte with set Co bit and A0 set to logic 0
Ver 1.9
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DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 26 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 Set column address of RAM. Set address to "00000000". Y[7:0]=00000000 (Y0 default is 00) DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 0 28 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Control byte with set Co bit and A0 set to logic 1 Data Write.
27
29 30 31
IIC INTERFACE start DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
restart Slave address for write Control byte with set Co bit and A0 set to logic 0 Set X address of RAM. Set address to "0000000".
32
33
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 0 0 0 0 0 0 0
Control byte with cleared Co bit and A0 set to logic 0
Ver 1.9
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ST7541 APPICATION NOTE
ST7541
Internal analog circuit Resolution : 129(128COM+ICOM)*128(SEG) Interface:8080 series OSC1:External for input (the same pin shoud be connected together, for example,pin246(D0) connect to pin247(D0) exclude power pin) PS0:VDD PS1:VSS PS2:VSS TA:VSS TB:VSS REF:VDD INTRS:VDD VR:OPEN VEXT:OPEN T0~T9:OPEN MF[2:0]:VDD OR VSS=(0,0,0) DS[1:0]:VDD OR VSS=(0,0) (MF[2:0]&DS[1:0] is ID of this IC, these pins cannot be left open) C=1uF
................
385
COM 31
1
COM30
COM 51
................
365
364 ..... .......
COM52 ..... ....... COM63 V0 V1 V2 V3 V4 VR VDD OSC1 VSS INTRS VDD VEXT VSS REF VDD T8~T0
VOUT_IN
VOUT_OUT
353 .......... ........... .......... ........... .......... ........... .......... ...........
351~352
350 349 348 347
345~346
344
342~343
341 340 31 32 33 COM0 COMS1 SEG0 339 338 337 336 335
326~334 320~325 314~319
313 ... ........... ........... ...................... ........ ... ........... ........... ...................... ........ 312 311 310 309 308 307 306
300~305 284~299 268~283 262~267 260~261 258~259 256~257 254~255 252~253
VDD DS1 DS0 MF0 MF1 MF2 TB TA VSS VSS2 VDD2 VDD D7 D6 D5 D4 D3 D2 D1 D0 E_RD RW_WR A0 RST CSB VSS PS2 PS1 PS0 VDD T9 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 VOUT D7 D6 D5 D4 D3 D2 D1 D0 E_RD RW_WR A0 RST CSB VSS VDD C 21 20 19 18 17 V0 V1 V2 V3 V4 C ... ........... .. CCC
160
161~164
SEG127
RESERVE
ST7541
COM64
250~251 248~249 246~247 244~245 242~243 240~241 238~239 236~237
165
235 .. ........... ........... ................................ ........ ........... .......... ...................... ..... 234 233 232 231 230
229 228
COMS2 COM127
196
COM95 C OM 96
................ COM 116
217
197
218
... ........... .. COM117 ................
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ST7541
Internal analog circuit Resolution : 129(128COM+ICOM)*128(SEG) Interface : 4 SPI OSC1:External for input (if use internal oscillator,OSC1 must be fixed to VDD) (the same pin shoud be connected together, for example,pin246(D0) connect to pin247(D0)) PS0:VSS PS1:VDD PS2:VSS TA:VSS TB:VSS REF:VDD INTRS:VDD VR:OPEN VEXT:OPEN T0~T9:OPEN MF[2:0]:VDD OR VSS=(0,0,0) DS[1:0]:VDD OR VSS=(0,0) (MF[2:0]&DS[1:0] is ID of this IC, these pins cannot be left open) C=1uF
................
385
COM31
1
COM30
COM51
................
365
364 ............
COM52 ............ COM63 V0 V1 V2 V3 V4 VR VDD OSC1 VSS INTRS VDD VEXT VSS REF VDD T8~T0
VOUT_IN
VOUT_OUT
353 .......................................... ..........................................
351~352
350 349 348 347
345~346
344
342~343
341 340 31 32 33 COM0 COMS1 SEG0 339 338 337 336 335
326~334 320~325 314~319
313 ....................................................... ....................................................... 312 311
VDD DS1 DS0 MF0 MF1 MF2 TB TA VSS VSS2 VDD2 VDD D7 D6 D5 D4 D3 D2 D1 D0 E_RD RW_WR A0 RST CSB VSS PS2 PS1 PS0 VDD T9 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A0 RST CSB VSS VDD V0 V2 V3 V4 OSC1 VOUT SID SCLK C C C C C V1
ST7541
SEG127
RESERVE
310 309 308 307 306
300~305 284~299 268~283 262~267 260~261 258~259 256~257 254~255 252~253
160
161~164
250~251 248~249 246~247 244~245 242~243 240~241 238~239 236~237
165
COM64
235 ........................................................ ........................................................ 234 233 232 231 230
229 228
COMS2 COM127
................
197
196
COM95 COM96
................ COM116
217
218
COM117
................
Ver 1.9
................
76/78
2007/9/3
ST7541
ST7541
Internal analog circuit Resolution : 129(128COM+ICOM)*128(SEG) Interface : I2C OSC1:External for input (the same pin shoud be connected together, for example,pin246(D0) connect to pin247(D0) exclude power pin) SA[1:0]:VDD OR VSS=(0,0) (SA[1:0] are Slave address of I2C)
................
PS0:VSS PS1:VSS PS2:VDD TA:VSS TB:VSS REF:VDD INTRS:VDD
VR:OPEN VEXT:OPEN T0~T9:OPEN MF[2:0]:VDD OR VSS=(0,0,0) DS[1:0]:VDD OR VSS=(0,0) (MF[2:0]&DS[1:0] is ID of this IC, these pins cannot be left open) C=1uF ; R=10K
385
COM31
1
COM30
COM51
................
365
364 ............
COM52 ............ COM63 V0 V1 V2 V3 V4 VR VDD OSC1 VSS INTRS VDD VEXT VSS REF VDD T8~T0
VOUT_IN
VOUT_OUT
353 ................. ...................... ... ................. ...................... ...
351~352
350 349 348 347
345~346
344
342~343
341 340 31 32 33 COM0 COMS1 SEG0 339 338 337 336 335
326~334 320~325 314~319
313 ...... ........... ...................................... ...... ........... ...................................... 312 311 310 309 308 307 306
300~305 284~299 268~283 262~267 260~261 258~259 256~257 254~255 252~253
VDD DS1 DS0 MF0 MF1 MF2 TB TA VSS VSS2 VDD2 VDD D7(SCL) D6(SDA_IN) D5(SDA_IN) D4(SDA_IN)
D3(SDA_OUT) D2(SDA_OUT)
ST7541
11 10 9 8 7 6 5 4
V0 V2 V3 V4 VOUT SCL SDA R R C C C C C V1
160
161~164
SEG127
RESERVE
250~251 248~249 246~247 244~245 242~243 240~241 238~239 236~237
D1(SA1) D0(SA0) E_RD RW_WR A0 RST CSB VSS PS2 PS1 PS0 VDD T9 2 1 VSS VDD 3 RST
165
COM64
235 ........................................................ ........................................................ 234 233 232 231 230
229 228
COMS2 COM127
........... .....
197
196
COM95 COM96
................ CO M116
217
218
COM117
................
Ver 1.9
........... .....
77/78
2007/9/3
ST7541
ST7541
Internal analog circuit Resolution : 129(128COM+ICOM)*128(SEG) Interface : 3 SPI OSC1:External for input (the same pin shoud be connected together, for example,pin246(D0) connect to pin247(D0) exclude power pin) PS0:VSS PS1:VDD PS2:VSS TA:VSS TB:VSS REF:VDD INTRS:VDD VR:OPEN VEXT:OPEN T0~T9:OPEN MF[2:0]:VDD OR VSS=(0,0,0) DS[1:0]:VDD OR VSS=(0,0) (MF[2:0]&DS[1:0] is ID of this IC, these pins cannot be left open) C=1uF
................
385
COM31
1
COM30
COM51
................
365
364 ............
COM52 ............ COM63 V0 V1 V2 V3 V4 VR VDD OSC1 VSS INTRS VDD VEXT VSS REF VDD T8~T0
VOUT_IN
VOUT_OUT
353 .......................................... ..........................................
351~352
350 349 348 347
345~346
344
342~343
341 340 31 32 33 COM0 COMS1 SEG0 339 338 337 336 335
326~334 320~325 314~319
313 ........................................ ............... ........................................ ............... 312 311 310 309 308 307 306
300~305 284~299 268~283 262~267 260~261 258~259 256~257 254~255 252~253
VDD DS1 DS0 MF0 MF1 MF2 TB TA VSS VSS2 VDD2 VDD D7 D6 D5 D4 D3 D2 D1 D0 E_RD RW_WR A0 RST CSB VSS PS2 PS1 PS0 VDD T9 4 3 2 1 RST CSB VSS VDD 7 6 5 VOUT SID SCLK C 12 11 10 9 8 V0 V2 V3 V4 C ................ C C C V1
160
161~164
SEG127
RESERVE
ST7541
COM64
250~251 248~249 246~247 244~245 242~243 240~241 238~239 236~237
165
235 ........................................................ ........................................................ 234 233 232 231 230
229 228
COMS2 COM127
197
196
COM95 C OM96
................ CO M116
217
218
................ COM117 ................
Ver 1.9
78/78
2007/9/3

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